Fully associative texture cache having content addressable memory and method for use thereof

A graphics processing system, comprising:

• a bus interface for coupling to a system bus;
• a graphics processor coupled to the bus interface to process graphics data;
• address and data busses coupled to the graphics processor to transfer address and graphics data to and from the graphics processor;
• and
• a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address, the cache memory comprising first and second memories coupled together by a plurality of activation lines, the first memory having a corresponding plurality of address detection units to store addresses and provide activation signals in response to receiving a matching address, and the second memory having a corresponding plurality of data storage locations, each data storage location coupled to a respective one of the plurality of address storage locations by a respective activation line to provide graphics data in response to receiving an activation signal from the respective address storage location.

A graphics processing system, comprising:

• a bus interface for coupling to a system bus;
• a graphics processor coupled to the bus interface to process graphics data;
• address and data busses coupled to the graphics processor to transfer address and graphics data to and from the graphics processor;
• and
• a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address, the cache memory comprising:
• a comparing means to compare memory addresses to a plurality of tag addresses stored in a corresponding plurality of memory locations;
• and
• an activating means to activate a storage location coupled to the memory location storing the matching memory address to provide requested graphics data.

A computer system, comprising:

• a system processor;
• a system bus coupled to the system processor;
• a system memory coupled to the system bus;
• and
• a graphics processing system coupled to the system bus, the graphics processing system, comprising:
• a bus interface for coupling to the system bus;
• a graphics processor coupled to the bus interface to process graphics data;
• address and data busses coupled to the graphics processor to transfer address and graphics data to and from the graphics processor;
• and
• a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address, the cache memory comprising first and second memories coupled together by a plurality of activation lines, the first memory having a corresponding plurality of address detection units to store addresses and provide activation signals in response to receiving a matching address, and the second memory having a corresponding plurality of data storage locations, each data storage location coupled to a respective one of the plurality of address storage locations by a respective activation line to provide graphics data in response to receiving an activation signal from the respective address storage location.

A method of retrieving graphics data in a graphics processing system, comprising:

• converting a relative address for a texel to a memory address at which requested graphics data for the texel is stored;
• comparing the memory address to a plurality of tag addresses stored in a corresponding plurality of memory locations of a content addressable memory;
• and
• activating a storage location coupled to the memory location storing the matching memory address to provide the requested graphics data.