Memory system and method for improved utilization of read and write bandwidth of a graphics processing system

A graphics processing system, comprising:

• an embedded memory array having at least three separate banks of memory for storing graphics data in memory pages, each memory bank having separate read and write ports in a single port configuration;
• a memory controller coupled to the read and write ports of each bank of memory and adapted to write post-processed data to a first bank of memory while reading data from a second bank of memory;
• and
• a synchronous graphics processing pipeline coupled to the memory controller to process graphics data read from the second bank of memory by the memory controller and to further provide post-processed graphics data to the memory controller to be written to the first bank of memory, the processing pipeline capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory.

A computer system, comprising:

• a system processor;
• a system bus coupled to the system processor;
• a system memory coupled to the system bus;
• and
• a graphics processing system coupled to the system bus, the graphics processing system, comprising:
• at least three banks of memory storing graphics data in memory pages, each bank of memory having separate read and write ports, the read and write ports inoperative simultaneously;
• a memory controller having input and output terminals coupled to the read and write ports of each bank of memory, respectively, and further having pre-process and post-process terminals, the memory controller adapted to read data from a first bank of memory and write post-processed data to a second bank of memory concurrently;
• and
• a synchronous graphics processing pipeline having input and output terminals coupled to the pre-process and post-process terminals, respectively, to process graphics data received from the memory controller and to provide post-processed graphics data back to the memory controller to be written to a bank of memory, the graphics processing pipeline having a data length sufficient to contain the graphics data of a memory page.

A method of processing graphics data, comprising:

• processing graphics data retrieved from a first bank of single ported memory through a synchronous graphics processing pipeline to produce post-processed graphics data;
• retrieving graphics data from a second bank of single ported memory;
• processing the graphics data retrieved from the second bank of memory through the synchronous graphics processing pipeline;
• and
• writing post-processed data back to the first bank of memory concurrently with the processing of the graphics data retrieved from the second bank of memory.

A method of processing graphics data, comprising:

• processing graphics data retrieved from a page of memory in a first bank of single ported memory through a synchronous graphics processing pipeline to produce post-processed graphics data;
• retrieving graphics data from a page of memory in a second bank of single ported memory;
• processing the graphics data retrieved from the page of memory in the second bank of memory through the synchronous graphics processing pipeline;
• and
• writing post-processed data back to the page of memory in the first bank of memory concurrently with the processing of the graphics data retrieved from the page of memory in the second bank of memory.