Electro-optical device, clock signal adjusting method and circuit therefor, producing method therefor, and electronic equipment
AssigneeSeiko Epson Corporation
InventorsShin Fujita, Tokuro Ozawa
Life of this patent
Estimating the term…
Abstract
The invention prevents shift register circuits from malfunctioning. A distribution circuit outputs a trailing trigger pulse DTP and a leading trigger pulse UTP. A trailing edge control circuit and a leading edge control circuit delay the trailing trigger pulse DTP and the leading trigger pulse UTP, respectively. The delay time of each of these control circuits can be set. These delay times are determined according to a threshold voltage of a TFT constituting a shift register. An inverted clock signal CLYINV is generated according to output signals of the control circuits. The shift register is driven by a clock signal CLY and an inverted clock signal CLYINV.
Claims29
A method of adjusting a clock signal in an electro-optical device having a display portion, which has a plurality of scanning lines, a plurality of data lines, and pixels provided respectively corresponding to intersections between said scanning lines and said data lines, and also having a shift register that sequentially shifts a start pulse according to a clock signal and an inverted clock signal, said electro-optical device structured to generate signals, which are supplied to said plurality of scanning lines or said plurality of data lines, according to each output signal of said shift register, said method being employed to adjust phases of the clock signal and the inverted clock signal, which are supplied to said shift register, said method comprising the steps of:
- detecting a threshold voltage of a transistor representative of at least one transistor of said shift register;
- and
- adjusting relative phases of the clock signal and the inverted clock signal according to the detected threshold voltage.
A method for use in an electro-optical device having a display portion, which has a plurality of scanning lines, a plurality of data lines, and pixels provided respectively corresponding to each of intersections between said scanning lines and said data lines, and also having a shift register that sequentially shifts a start pulse according to a clock signal and an inverted clock signal, said electro-optical device structured to generate signals, which are supplied to said plurality of scanning lines or said plurality of data lines, according to each output signal of said shift register, said method being employed to adjust phases of the clock signal and the inverted clock signal, which are supplied to said shift register, said method comprising the steps of:
- detecting a threshold voltage and an ON-current of a transistor representative of at least one transistor of said shift register;
- and
- adjusting relative phases of the clock signal and the inverted clock signal according to the detected threshold voltage and ON-current.
A clock signal adjusting circuit for use in an electro-optical device having a display portion, which has a plurality of scanning lines, a plurality of data lines, and pixels provided respectively corresponding to intersections between said scanning lines and said data lines, and also having a shift register that sequentially shifts a start pulse according to a clock signal and an inverted clock signal, said electro-optical device structured to generate signals, which are supplied to said plurality of scanning lines or said plurality of data lines, according to each output signal of said shift register, said clock signal adjusting circuit being used to adjust phases of the clock signal and the inverted clock signal, which are supplied to said shift register, said clock signal adjusting circuit comprising:
- a first phase adjusting portion that adjusts relative phases of a leading edge of the clock signal and a trailing edge of the inverted clock signal according to a threshold voltage of a transistor representative of at least one transistor of said shift register;
- and
- a second phase adjusting portion that adjusts relative phases of a trailing edge of the clock signal and a leading edge of the inverted clock signal according to a threshold voltage of a transistor representative of at least one transistor of said shift register.
A clock signal adjusting circuit for use in an electro-optical device having a display portion, which has a plurality of scanning lines, a plurality of data lines, and pixels provided respectively corresponding to each of intersections between said scanning lines and said data lines, and also having a shift register that sequentially shifts a start pulse according to a clock signal and an inverted clock signal, said electro-optical device structured to generate signals, which are supplied to said plurality of scanning lines or said plurality of data lines, according to each output signal of said shift register, said clock signal adjusting circuit being used to adjust phases of the clock signal and the inverted clock signal, which are supplied to said shift register, said clock signal adjusting circuit comprising:
- a first phase adjusting portion that adjusts relative phases of a leading edge of the clock signal and a trailing edge of the inverted clock signal according to a threshold voltage and an ON-current of a transistor representative of at least one transistor of said shift register;
- and
- a second phase adjusting portion that adjusts relative phases of a trailing edge of the clock signal and a leading edge of the inverted clock signal according to a threshold voltage and an ON-current of a transistor representative of at least one transistor of said shift register.
A method of producing an electro-optical device having a display panel, which has a display portion including a plurality of scanning lines, a plurality of data lines, and pixels respectively provided correspondingly to intersections between said scanning lines and said data lines, and also has a driving portion that drives said display portion by using a shift register, and also having a clock signal generating circuit enabled to generate a clock signal and an inverted clock signal, which are supplied to said shift register, and to adjust relative phases of the clock signal and the inverted clock signal, said method comprising the steps of:
- manufacturing said display panel;
- measuring a threshold voltage of transistor representative of at least one transistor of said shift register of said manufactured display panel;
- and
- adjusting the phases of the clock signal and the inverted clock signal according to the measured threshold voltage.
Dependencies are inferred from the claim text.