Digital driver and display device

A display device comprising:

• a digital video divider circuit for lowering to 1/x frequency of digital video data wherein x stands for a natural number of 2 or greater;
• a pair of source drivers each connected to said digital video divider circuit;
• a shift register circuit formed in each of said source drivers and including a register circuit at the first stage, a register circuit at the second stage, . . . , a register circuit at the (n−1)th stage and a register circuit at the nth stage (wherein n stands for a natural number);
• and
• a latch circuit array formed in each of said source drivers and including a first latch circuit, a second latch circuit, . . . , an (n−1)th latch circuit and an nth latch circuit,
• wherein a first digital data, a second digital data, . . . , an (n−1)th digital data and an nth digital data are successively inputted to said register circuit at the first stage,
• wherein the output of said register circuit at the first stage, the output of said register circuit at the second stage, . . . , the output of said register circuit at the (−1)th stage and the output of said register circuit at the nth stage are respectively sent out to said first latch circuit, said second latch circuit, . . . , said (n−1)th latch circuit and said nth latch circuit,
• wherein the instant said first digital data is inputted to said register circuit at the nth stage, the oscillation of a clock signal inputted to said shift register circuit stops, and said nth digital data, said (n−1)th digital data, . . . , said second digital data and said first digital data which are respectively held in said register circuit at the first stage, said register circuit at the second stage, . . . , said register circuit at the (n−1)th stage and said register circuit at the nth stage are respectively read into said first latch circuit, said second latch circuit, . . . , said (n−1)th latch circuit and said nth latch circuit.

A display device comprising:

• TFTs disposed in a matrix shape;
• a pair of source drivers;
• a gate driver;
• and
• a digital video divider circuit connected to each of said source drivers,
• wherein said digital video divider circuit lowers to 1/x frequency of digital video data wherein x stands for a natural number of 2 or greater,
• wherein each of said source drivers comprises a shift register circuit which includes a plurality of register circuits, a first latch circuit array which includes a plurality of first latch circuits and is connected to the shift register circuit, a first selector circuit connected to the first latch circuit array, a second latch circuit array which includes a plurality of second latch circuits and is connected to the first selector circuit, a second selector circuit connected to the second latch circuit array, and a D/A converter circuit connected to the second selector circuit
• wherein digital data divided in said digital video divider circuit are inputted to said shift register circuit,
• wherein said digital data successively shift through said plurality of register circuits, and
• wherein said digital data outputs from the corresponding ones of said register circuits are inputted to said plurality of first latch circuits.

A display device comprising:

• TFTs disposed in a matrix shape;
• a pair of source drivers;
• a gate driver;
• and
• a digital video divider circuit connected to each of said source drivers,
• wherein said digital video divider circuit lowers to 1/x frequency of digital video data wherein x stands for a natural number of 2 or greater,
• wherein said source driver comprises a shift register circuit which includes a register circuit at the first stage, a register circuit at the second stage, . . . , a register circuit at the (n−1)th stage and a register circuit at the nth stage (wherein n stands for a natural number) and a latch circuit array which includes a first latch circuit, a second latch circuit, . . . , an (n−1)th latch circuit and an nth latch circuit,
• wherein first digital data, second digital data, . . . , (n−1)th digital data and nth digital data are successively inputted to said register circuit at the first stage,
• wherein the output of said register circuit at the first stage, the output of said register circuit at the second stage, . . . , the output of said register circuit at the (n−1)th stage and the output of said register circuit at the nth stage are respectively sent out to said first latch circuit, said second latch circuit, . . . , said (n−1)th latch circuit and said nth latch circuit, and
• wherein the instant said first digital data is inputted to said register circuit at the nth stage, the oscillation of a clock signal inputted to said shift register circuit stops, so that said nth digital data, said (n−1)th digital data, . . . , said second digital data and said first digital data which are respectively held in said register circuit at the first stage, said register circuit at the second stage, . . . , said register circuit at the (n−1)th stage and said register circuit at the nth stage are respectively taken into said first latch circuit, said second latch circuit, . . . , said (n−1)th latch circuit and said nth latch circuit.