Analog-to-digital converter which is substantially independent of capacitor mismatch

A method for converting an analog input signal to a digital signal using an amplifier, the method comprising:

• (a) sampling the analog input signal onto a first capacitor and a complement of the analog input signal onto a second capacitor;
• (b) providing the sampled analog input signal at a first input terminal of the amplifier by controllably coupling the first capacitor between the amplifier output and the first input terminal in a unity gain feedback configuration;
• (c) providing the sampled complemented analog input signal, level shifted by one of a plurality of selectable reference voltages, at a second input terminal of the amplifier by controllably coupling the second capacitor between a selected one of the reference voltages and the second input terminal of the amplifier;
• and
• (d) adding the sampled analog input signal to an inverted version of the sampled complemented analog input signal and subtracting the selected one of the reference voltages to provide a residue signal available for use in subsequent conversion stages.

An analog-to-digital converter (ADC) stage for use in converting a differential analog input signal to a digital signal, comprising:

• a first single-ended amplifier arranged in a unity feedback configuration;
• first and second sampling means for sampling the differential analog input signal at a first time;
• first switch means coupled to the first and second sampling means and to the first amplifier for providing the sampled differential analog input signal to first and second input terminals of the first amplifier, and to provide a level-shift voltage to offset the sampled differential analog input signal at the second input terminal of the first amplifier, at a second time;
• a second single-ended amplifier arranged in a unity feedback configuration;
• third and fourth sampling means for sampling the differential analog input signal at the first time;
• second switch means coupled to the third and fourth sampling means and to the second amplifier for providing the sampled differential analog input signal to first and second input terminals of the second amplifier, and to provide a level-shift voltage to offset the sampled differential analog input signal at the second input terminal of the second amplifier;
• and
• wherein the first and second amplifiers respectively add the respective sampled differential analog input signals and subtract the level-shift voltage, and collectively output a differential output signal at the second time.

An analog-to-digital converter (ADC) stage for use in differential ADCs, comprising:

• (a) a first sample and hold circuit, comprising:
• (1) a first single-ended amplifier having first and second input terminals, and an output terminal to output a first half of a differential residue signal;
• (2) a first sampling circuit comprising first and second capacitors to respectively store first and second voltages of a differential input signal at a first time;
• (3) a first switch circuit coupled to the first amplifier and to the first sampling circuit to switch the first capacitor between the first amplifier's output terminal and its first input terminal, and to switch the second capacitor between a selectable level-shift voltage and the first amplifier's second input terminal;
• (4) wherein the first amplifier adds the first and second voltages, subtracts a selected one of the selectable level-shift voltages, and outputs the first half of the differential residue signal at a second time;
• (b) a second sample and hold circuit, comprising:
• (1) a second single-ended amplifier having first and second input terminals, and an output terminal to output a second half of the differential residue signal;
• (2) a second sampling circuit comprising third and fourth capacitors to respectively store the second and first voltages of the differential input signal at the first time;
• (3) a second switch circuit coupled to the second amplifier and to the second sampling circuit to switch the third capacitor between the second amplifier's output terminal and its first input terminal, and to switch the fourth capacitor between the selectable level-shift voltage and the second amplifier's second input terminal;
• and
• (4) wherein the second amplifier adds the second and first voltages, subtracts a selected one of the selectable level-shift voltages, and outputs the second half of the differential residue signal at the second time.

An algorithmic analog-to-digital converter (ADC) to convert an input voltage signal to a digital data signal, comprising:

• (a) an ADC stage to receive the input voltage signal and to create an analog ADC residue signal, the ADC stage comprising:
• (1) an amplifier having first and second input terminals, and an output terminal;
• (2) first and second capacitances coupled to sample the input voltage signal and a complemented input voltage signal respectively in response to a first clock phase;
• (3) a first switch circuit coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to a second clock phase;
• (4) a second switch circuit coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier in response to the second clock phase;
• (5) a sub-ADC circuit coupled to receive the input voltage signal, and in response, to provide a digital data subset of the digital data signal;
• (6) a decoder coupled to the sub-ADC circuit to receive the digital data subset and to select one of a plurality of reference voltages to add to the inverted version of the complemented input voltage in response thereto;
• (7) wherein the amplifier outputs the analog ADC residue signal by adding the sampled input voltage signal to the inverted version of the sampled complemented input voltage as shifted by the level shifting circuit;
• and
• (b) a feedback loop to provide the analog ADC residue signal as the input voltage signal to the ADC stage for N−1 additional cycles of an N-cycle analog-to-digital conversion.

A pipelined analog-to-digital converter (ADC) to convert an input voltage signal to a digital data signal, comprising:

• (a) a plurality of N−1 pipelined ADC stages, wherein a first pipelined ADC stage receives the input voltage signal, and the remaining N−1 pipelined ADC stages receive an analog ADC residue signal from a prior ADC stage as its input voltage signal, each of the plurality of ADC stages comprising:
• (1) an amplifier having first and second input terminals, and an output terminal;
• (2) first and second capacitances coupled to sample the input voltage signal and a complemented input voltage signal respectively in response to a first clock phase;
• (3) a first switch circuit coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to a second clock phase;
• (4) a second switch circuit coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier in response to the second clock phase;
• (5) a sub-ADC circuit coupled to receive the input voltage signal, and in response, to provide a digital data subset of the digital data signal;
• (6) a decoder coupled to the sub-ADC circuit to receive the digital data subset and to select one of a plurality of reference voltages to add to the inverted version of the complemented input voltage in response thereto;
• (7) wherein the amplifier outputs the analog ADC residue signal by adding the sampled input voltage signal to the inverted version of the sampled complemented input voltage as shifted by the level shifting circuit;
• and
• (b) an Nth pipelined ADC stage coupled to the N−1 ADC stage to resolve least significant bits of the digital data signal.