Synchronizing circuits and methods for parallel path analog-to-digital converters
AssigneeSamsung Electronics Co., Ltd.
InventorSoo-Hyoung Lee
Life of this patent
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Abstract
An Analog-to-Digital (A/D) converter includes signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal. A respective signal path includes a comparator. A synchronizing circuit is responsive to a clock signal and outputs of the comparators, to generate a respective delayed clock signal that is applied to a respective comparator. A respective signal path also includes a respective decoder that is responsive to a respective comparator and to the clock signal.
Claims14
An analog-to-digital (A/D) converter, comprising:
- a plurality of signal paths that are responsive to an analog input signal, to generate a multi-bit digital output signal therefrom;
- and
- a circuit that is configured to generate delayed clock signals, which have delay times different from each other according to phase differences, by feeding-back and detecting a phase of signals in the signal paths, and configured to correct the signals in the signal paths by using the delayed clock signals.
An analog-to-digital (A/D) converter, comprising:
- a clock buffer that is configured to receive and buffer an external clock signal, to thereby generate an internal clock signal;
- a plurality of process routines that are configured to receive and process an analog input signal;
- a plurality of comparators that are configured to receive analog signals from the plurality of process routines and to compare the received analog signals with a reference voltage, to thereby generate digital signals therefrom under control of a respective one of delayed clock signals;
- a plurality of decoders that are configured to receive the digital signals from the plurality of comparators and to convert the received digital signals into a code format, to thereby generate converted digital signals;
- and
- a synchronizing circuit that is configured to receive the internal clock signal from the clock buffer and the digital signals from the plurality of comparators and to generate the respective delayed clock signals therefrom.
An analog-to-digital (A/D) converter, comprising:
- a plurality of signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal therefrom, a respective signal path including therein a comparator;
- and
- a synchronizing circuit that is responsive to a clock signal and outputs of the comparators, to generate a respective delayed clock signal that is applied to a respective comparator.
A synchronizing method for an analog-to-digital (A/D) converter that includes a plurality of signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal therefrom, a respective signal path including therein a comparator, the synchronizing method comprising:
- generating a plurality of delayed clock signals from a clock signal and outputs of the comparators;
- and
- applying a respective one of the delayed clock signals to a respective comparator.
Dependencies are inferred from the claim text.