System and a method for an ultra-low delay MPEG-syntax video codec
AssigneeScopus Network Technologies Ltd.
InventorAmichay Amitay
Life of this patent
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Abstract
A system for compressed digital video bitstreams, in which an I-frame may precede a plurality of P-frames slices, wherein the system includes an encoder to encode the bits for each successive P-frame slice. The system also includes a decoder buffer, where the bits enter at a fixed rate and a decoder, which uses the extracted bits to decode each frame and display each frame. The delay is chosen at a fixed rate between 10 msec and 100 msec.
Claims8
A system for processing a compressed digital video bitstream formatted as a plurality of P-field slices, which may be preceded by a single I-frame, the system comprising:
- an encoder to encode the bits for each successive P-field slice, said encoder introducing an encoder delay component;
- and
- a decoder, which includes a buffer in which said bits are placed at a fixed rate, and which extracts said bits to decode each field-slice and display each field-slice, said decoder introducing a decoder delay component,
- wherein the total delay of said encoder and decoder delay components is chosen as a fixed value between 10 msec and 100 msec.
A method for processing a compressed digital video bit stream formatted as a plurality of P-Field slices, which may be preceded by a single I-frame, the method comprising:
- encoding of bits associated with the bitstream for each successive P-field slice, thereby introducing an encoder delay component;
- and
- decoding by placing said bits in a decoder buffer at a fixed rate, and extracting said bits to decode each P-field slice and display each P-field slice, thereby introducing a decoder delay component,
- wherein the total delay of said encoder and decoder delay components is chosen as a fixed value between 10 msec and 100 msec.
Dependencies are inferred from the claim text.