Post-silicon phase offset control of phase locked loop input receiver

A phase locked loop, comprising:

• an input receiver adapted to receive as input a system clock and a feedback clock and is responsive to an adjustment circuit operatively connected to the input receiver, wherein the input receiver comprises circuitry configured to modulate a delay of the system clock and a delay of the feedback clock;
• a phase frequency detector responsive to the input receiver;
• a bias generator responsive to the phase frequency detector;
• and
• a voltage controlled oscillator responsive to the bias generator, wherein the voltage controlled oscillator is adapted to output an output clock.

A method for post-silicon adjustment of a phase locked loop, comprising:

• inputting a system clock and a feedback clock to an input receiver, wherein the input receiver comprises circuitry configured to modulate a delay of the system clock and a delay of the feedback clock;
• selectively adjusting a delay of any one of the system clock and the feedback clock using an adjustment circuit operatively connected to the input receiver;
• comparing the system clock and the feedback clock;
• and
• generating a voltage to a voltage controlled oscillator dependent on the comparing, wherein the voltage controlled oscillator generates an output clock.

An integrated circuit, comprising:

• phase locked loop means for generating an output clock, wherein the phase locked loop means comprises:
• input means for inputting a system clock and a feedback clock, wherein the input means comprises means for modulating a delay of the system clock and the feedback clock,
• charge pumping means for generating a control voltage, wherein the charge pumping means is responsive to the input means,
• bias generating means for generating a bias voltage, wherein the bias generating means is responsive to the control voltage, and
• oscillator means for generating the output clock, wherein the oscillator means is responsive to the bias voltage;
• and
• adjusting means for adjusting a delay of any one of the system clock and the feedback clock, wherein the adjusting means is operatively connected to the input means.