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AssigneeNokia Corporation
InventorsMika Salmi, Mikael Svard
Estimating the term…
A resampling technique is used to reduce the noise and improve the signal quality in the output of a prescaler circuit (10). The resampling of the output of a last frequency divider stage is accomplished using at least one flip/flop (FF) (e.g., a D-type FF 18) that is clocked by a signal obtained from the input of the prescaler. This reduces or eliminates the noise caused by edge jitter in the output of the prescaler, as well as the effect of spurious signals generated by the prescaler. These teachings can be used in integer N PLLs and in fractional N PLLs, as well as in single and programmable dual or multi-modulus prescalers. Using this technique the current consumption of the prescaler frequency dividers (12, 14, 16) need not be increased in an effort to reduce the prescaler noise, thereby conserving current in battery powered and other applications.
A phase locked loop comprising a phase comparator generating an output signal that is used to drive a voltage controlled oscillator, and a modulus N prescaler circuit coupled to an output of said voltage controlled oscillator, said prescaler circuit comprising an input node for coupling to said output of said voltage controlled oscillator for receiving an input signal having a characteristic frequency to be divided by N, said input signal comprising two clock input signals, an output node for outputting a frequency divided signal that is coupled to said phase comparator, and a plurality of divider stages coupled between the input node and the output node for dividing the input signal by N, and further comprising at least one resampling stage coupled to an output of at least one of said divider stages for receiving an output signal therefrom, said output signal comprising two output signals, and for synchronizing edges of the output signal to edges of the input signal, thereby reducing temporal ambiguity in the occurrence of the edges of the output signal, where said at least one resampling stage is comprised of a flip-flop having a data input coupled to said output of said at least one of said divider stages and a clock input coupled to said input node for being clocked with said output of said voltage controlled oscillator.
A method for reducing power consumption in a frequency source of a mobile station, comprising:
A method to operate a phase locked loop as part of a frequency source to generate a signal having a desired frequency, comprising:
A mobile station, comprising a radio frequency (RF) transceiver that is tunable using a frequency synthesizer that comprises a phase lock loop (PLL), said PLL comprising a phase comparator for comparing a frequency divided oscillator output signal to a frequency divided voltage controlled oscillator (VCO) output signal and generating in accordance with said comparison a control signal that is applied via a loop filter to said VCO, further comprising a prescaler block disposed between an output of said VCO and an input of a frequency divider, said prescaler block comprising a frequency divider block having an input coupled to said output of said VCO, the output of the VCO comprising two output clock signals, said frequency divider block having an output for outputting a frequency divided signal, said prescaler block further comprising a flip-flop having an input coupled to said output of said frequency divider block and a clock input coupled to said output of said VCO, the output of said frequency divider block comprising two frequency divided output signals, said flip-flop operating to cause said prescaler block to output to said frequency divider a prescaled VCO signal having edge transitions that are synchronized to edge transitions of the VCO output signal.
Dependencies are inferred from the claim text.