Power amplifier
AssigneeAtheros Communications, Inc.
InventorAli Tabatabaei
Life of this patent
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Abstract
A system and method are disclosed for providing amplification to an input signal. The amplifier comprises an amplification stage configured to provide a gain to an input signal and to produce an amplified output, wherein the amplification stage includes an interface configured to receive a biasing voltage. The amplifier also comprises a peak detection feedback network coupled to the amplification stage configured to adjust the biasing voltage, whereby the peak detection feedback network controls the gain of the amplifier.
Claims21
An amplifier comprising:
- an amplification stage configured to provide a gain to an input signal and to produce an amplified output;
- wherein the amplification stage includes an interface configured to receive a biasing voltage;
- and
- a peak detection feedback network coupled to the amplification stage configured to adjust the biasing voltage;
- wherein:
- the peak detection feedback network controls the gain based on feedback of the amplified output;
- the amplification stage includes a first transistor coupled with a second transistor and wherein the first transistor and second transistor are connected in a cascode configuration and;
- the first transistor includes an input interface configured to receive the input signal and the second transistor includes an output interface configured to send the amplified output.
An amplifier comprising:
- an amplification stage configured to provide a gain to an input signal and to produce an amplified output;
- wherein the amplification stage includes an interface configured to receive a biasing voltage;
- and
- a peak detection feedback network coupled to the amplification stage configured to adjust the biasing voltage;
- wherein:
- the peak detection feedback network controls the gain based on feedback of the amplified output;
- the amplification stage includes a first transistor coupled with a second transistor and wherein the first transistor and second transistor are connected in a cascode configuration;
- the first transistor includes an input interface configured to receive the input signal and the second transistor includes an output interface configured to send the amplified output;
- and
- the peak detection feedback network is coupled between the input interface and the output interface.
An amplifier comprising:
- an amplification stage configured to provide a gain to an input signal and to produce an amplified output;
- wherein the amplification stage includes an interface configured to receive a biasing voltage a first transistor and second transistor connected in a cascode configuration;
- and
- a peak detection feedback network coupled to the amplification stage configured to adjust the biasing voltage;
- wherein the peak detection feedback network controls the gain based on feedback of the amplified output;
- and the peak detection feedback network includes:
- an input peak detector configured to detect an input amplitude;
- an attenuator configured to attenuate the amplified output;
- an output peak detector configured to detect the attenuated output amplitude;
- a differential amplifier configured to amplify the difference between the input amplitude and the attenuated output amplitude;
- wherein:
- the differential amplifier is coupled to the interface configured to receive a biasing voltage;
- the input peak detector includes a diode and a capacitor coupled to the diode;
- and
- the output peak detector includes a diode and a capacitor coupled to the diode.
An amplifier comprising:
- an amplification stage configured to provide a Rain to an input signal and to produce an amplified output;
- wherein the amplification stage includes an interface configured to receive a biasing voltage;
- and
- a peak detection feedback network coupled to the amplification stage configured to adjust the biasing voltage;
- wherein the peak detection feedback network controls the gain based on feedback of the amplified output;
- and the amplification stage comprises a pair of symmetrical amplifiers including a first symmetrical amplifier and a second symmetrical amplifier;
- wherein:
- a first radio frequency input is applied to the first symmetrical amplifier;
- a second radio frequency input is applied to the second symmetrical amplifier;
- and
- the second radio frequency input has a phase offset from the first radio frequency input.
An amplifier comprising:
- an amplification stage configured to provide a gain to an input signal and to produce an amplified output;
- wherein the amplification stage includes an interface configured to receive a biasing voltage;
- and
- a peak detection feedback network coupled to the amplification stage configured to adjust the biasing voltage;
- wherein the peak detection feedback network controls the gain based on feedback of the amplified output;
- and the amplification stage comprises a pair of symmetrical amplifiers including a first symmetrical amplifier and a second symmetrical amplifier;
- wherein a first radio frequency input is applied to the first symmetrical amplifier;
- a second radio frequency input is applied to the second symmetrical amplifier;
- the second radio frequency input has a phase offset from the first radio frequency input;
- the first symmetrical amplifier and the second symmetrical amplifier are coupled via a plurality of transformers;
- and the peak detection feedback network is coupled to the first and second amplification stages at a junction that is an AC ground.
Dependencies are inferred from the claim text.