Differential amplifier with input gate oxide breakdown avoidance

A method of making an integrated circuit comprising:

• forming a differential amplifier having a first input terminal, a second input terminal, a first input transistor, and a second input transistor, wherein the first input terminal is coupled to a gate node of the first input transistor and the second input terminal is coupled to the gate node of the second input transistor, and
• forming a pull-up circuit comprising:
• a first transistor having a source node coupled to a core voltage node;
• a second transistor coupled in series with the first transistor such that a source node of the second transistor is coupled to the drain and gate nodes of the first transistor, and
• a third transistor coupled in series with the first transistor and in parallel with the second transistor such that a source node of the third transistor is coupled to the drain and gate nodes of the first transistor,
• wherein a drain node of the second transistor is coupled to the drain node of the first input transistor and a drain node of the third transistor is coupled to the drain node of the second input transistor.

An integrated circuit comprising:

• first and second input terminals for receiving respective first and second input signals;
• a differential pair of transistors each coupled to a respective one of the first and second input terminals;
• a first bia circuit coupled to the differential pair of transistors for control node voltages associated with the differential pair of transistors when both first and second input signals fall within a first range;
• a second bias circuit coupled to the differential pair of transistors, for limiting, when at least one of the first and second input signals falls outside the first range, a voltage across one or both of the differential pair of transistors to a maximum voltage smaller in magnitude than otherwise allowed to develop by the first bias circuit acting alone;
• and
• wherein the first bias circuit includes a current mirror.

An integrated circuit comprising:

• first and second input terminals for receiving respective first and second input signals;
• a differential pair of transistors, each coupled to a respective one of the first and second input terminals;
• a first bias circuit coupled to the differential pair of transistors for controlling node voltage associated with the differential pair of transistors when both first and second input signals fall within a first range;
• a second bias circuit coupled to the differential pair of transistors or limiting, when at least one of the first and second input signals falls outside the first range, a voltage across one or both of the differential pair of transistors to a maximum voltage smaller in magnitude than otherwise allowed to develop by the first bias circuit acting alone;
• wherein the second bias circuit is a voltage limiting circuit;
• and
• wherein the voltage limiting circuit includes a current source coupled in series to a first and second diode-connected transistor, the first diode-connected transistor coupled in parallel to the second diode-connected transistor.

An integrated circuit comprising:

• first and second input terminals for receiving respective first and second input signals;
• a differential pair of transistors, each coupled to a respective one of the first and second input terminals;
• a first bias circuit coupled to the differential pair of transistors for controlling node voltages associated with the differential pair of transistors when both first and second input signals fall within a first range;
• a second bias circuit coupled to the differential pair of transistors, for limiting when at least one of the first and second input signals falls outside the first range, a voltage across one or both of the differential pair of transistors to a maximum voltage smaller in magnitude than otherwise allowed to develop by the first bias circuit acting alone;
• and
• wherein the second bias circuit includes
• a first transistor having a first node coupled to a core voltage node;
• a second transistor coupled in series with the first transistor such that a first node of the second transistor is coupled to a second and third node of the first transistor, and
• a third transistor coupled in series with the first transistor and in parallel with the second transistor such that a first node of the third transistor is coupled to the second and third nodes of the first transistor,
• wherein a second node of the second transistor is coupled to the second node of the first input transistor and a second node of the third transistor is coupled to the second node of the second input transistor.