Fast-settling DC offset removal circuits with continuous cutoff frequency switching
AssigneeHyperband Communication, Inc.
InventorsKanyu Cao, Tung-Shan Chen, Hongyu Li, Chieh-Yuan Chao
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Abstract
A fast-setting DC offset removal circuit with continuous cutoff frequency switching is disclosed. In the preferred embodiment, the circuit is implemented using a pair of RC filters for receiving a differential signal pair and a continuous, variable resistance control circuit. The control circuit can be current-controlled or voltage controlled to provide fast settling of the received signal and the removal of the DC offset components. Additionally, by using a current-controlled control circuit, the cutoff frequency of the RC filter can be ramped from high to low in a continuous manner, thereby minimizing the generation of DC offsets.
Claims12
A circuit for fast settling of received differential signal pair, comprising:
- a first capacitor having a first end connected to a first input node and a second end connected to a first output node;
- a second capacitor having a first end connected to a second input node and a second end connected to a second output node;
- a first continuously variable resistor having a first end connected to said first output node and a second end connected to a common voltage source;
- a second continuously variable resistor having a first end connected to said second output node and a second end connected to said common voltage source;
- and
- a control circuit for controlling said first continuously variable resistor and said second continuously variable resistor.
A circuit for fast settling of received differential signal pair, comprising:
- a first capacitor having a first end connected to a first input node and a second end connected to a first output node;
- a second capacitor having a first end connected to a second input node and a second end connected to a second output node;
- a first resistor having a first end connected to said first output node and a second end connected to a common voltage source;
- a first resistance transistor having a first node connected to said first output node, a second node connected to said common voltage source and a gate node;
- a second resistor having a first end connected to said second output node and a second end connected to said common voltage source;
- a second resistance transistor having a first node connected to said second output node, a second node connected to said common voltage source and a gate node;
- a mirror transistor having a first node, a second node connected to said common voltage source, and a gate node connected to said gate node of said first resistance transistor and said gate node of said second resistance transistor;
- a control transistor having a first node connected to the gate node of said mirror transistor, a second node connected to said first node of said mirror transistor, and a gate node connected to a bias voltage source;
- and
- a control current generation sub-circuit connected to said first node of the control transistor.
Dependencies are inferred from the claim text.