Clock generation circuit and clock conversion circuit
AssigneeSony Corporation
InventorTetsumasa Meguro
Life of this patent
Estimating the term…
Abstract
A clock generation circuit for generating clocks having a plurality of frequencies by which a suitable frequency for each task can be supplied such that the power consumption is reduced. A clock generation unit is provided for generating a clock with a constant frequency, with a counter operating in synchronization with the clock for counting pulses of the clock, a comparator for comparing a counter value of the counter with the number of pulses of a clock having a desired frequency, and an output gate for controlling the supply and stopping of pulses of the clock input from the clock generation unit based on a comparison result of the comparator.
Claims9
A clock generation circuit, comprising:
- a clock generation unit for generating a clock with a constant frequency;
- a first counter for counting in synchronization with said clock;
- a second counter for counting in synchronization with said clock every time said first counter overflows;
- a comparator for comparing the counter value of said second counter with a value corresponding to a frequency difference between a frequency of said clock and a desired frequency;
- and
- an output gate for controlling the supply and stopping of pulses of said clock based on a comparison result of said comparator and outputting a clock whose frequency has become the same as the desired frequency.
A clock generation circuit, comprising:
- a clock generation unit for generating a clock with a constant frequency;
- a first counter for counting in synchronization with said clock;
- a second counter for counting in synchronization with said clock every time said first counter overflows;
- a conversion circuit for performing data conversion on a counter value of said second counter and outputting the same;
- a comparator for comparing an output value of said conversion circuit with a value corresponding to a frequency difference between a frequency of said clock and a desired frequency every time said first counter overflows;
- and
- an output gate for controlling the supply and stopping of pulses of said clock based on a comparison results of said comparator and outputting a clock whose frequency has become the same as the desired frequency.
A clock conversion circuit, comprising:
- a first counter for counting in synchronization with a clock;
- a second counter for counting in synchronization with said clock every time said first counter overflows;
- a comparator for comparing a counter value of said second counter with a value corresponding to a frequency difference between a frequency of said clock and a desired frequency;
- and
- an output gate for controlling the supply and stopping of pulses of said clock based on a comparison result of said comparator and outputting a clock whose frequency has become the same as the desired frequency.
A clock conversion circuit, comprising:
- a first counter for counting in synchronization with a clock;
- a second counter for counting in synchronization with said clock every time said first counter overflows;
- a conversion circuit for performing data conversion on the counter value of said second counter and outputting the same;
- a comparator for comparing an output value of said conversion circuit with a value corresponding to a frequency difference between a frequency of said clock and a desired frequency;
- and
- an output gate for controlling the supply and stopping of pulses of said clock based on a comparison result of said comparator and outputting a clock whose frequency has become the same as the desired frequency.
Dependencies are inferred from the claim text.