Conditional clock buffer circuit
AssigneeBroadcom Corporation
InventorBrian J. Campbell
Life of this patent
Estimating the term…
Abstract
A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit includes a first circuit coupled to receive the clock input and a second circuit coupled to receive the clock input and the condition signal. The first circuit is configured to generate a first state on the clock output responsive to a first phase of the clock input. The second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input. In one implementation, one or more of the conditional clock buffer circuits may be included in a clock tree. The clock tree may also include one or more levels of buffering.
Claims22
A conditional clock buffer circuit having a clock output and coupled to receive a clock input and a condition signal, the conditional clock buffer circuit comprising:
- a first circuit coupled to receive the clock input and coupled to a first node within the conditional clock buffer circuit, the first circuit configured to generate a first state on the first node responsive to a first phase of the clock input;
- a second circuit coupled to receive the clock input and the condition signal and coupled to the first node, wherein the second circuit is configured to conditionally generate a second state on the first node during a condition window within a second phase of the clock input, wherein the condition window excludes at least a portion of the second phase, and wherein the second circuit is configured to conditionally generate the third state responsive to the condition signal during the condition window;
- and
- a third circuit coupled to the first node and to the clock output, the third circuit configured to generate a third state on the clock output responsive to the first state on the first node and configured to generate a fourth state on the clock output responsive to the second state on the first node.
A clock tree comprising:
- one or more levels of buffering coupled to receive an input clock and output a buffered clock;
- and
- a plurality of conditional clock buffer circuits coupled to receive the buffered clock and a condition signal, at least some of the conditional clock buffer circuits receiving different condition signals than other ones of the conditional clock buffer circuits, each conditional clock buffer circuit having a clock output and including:
- a first circuit coupled to receive the buffered clock and coupled to a first node within the conditional clock buffer circuit, the first circuit configured to generate a first state on the first node responsive to a first phase of the buffered clock;
- a second circuit coupled to receive the buffered clock and the condition signal and coupled to the first node, wherein the second circuit is configured to conditionally generate a second state on the first node during a condition window within a second phase of the buffered clock, wherein the condition window excludes at least a portion of the second phase, and wherein the second circuit is configured to conditionally generate the third state responsive to the condition signal during the condition window;
- and
- a third circuit coupled to the first node and to the clock output, the third circuit configured to generate a third state on the clock output responsive to the first state on the first node and configured to generate a fourth state on the clock output responsive to the second state on the first node.
A computer accessible medium comprising one or more data structures which are operated upon by a program executable on a computer system, the program operating on the data structures to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structures, the circuitry described in the data structures including a conditional clock buffer circuit having a clock output and coupled to receive a clock input and a condition signal, the conditional clock buffer circuit comprising:
- a first circuit coupled to receive the clock input and coupled to a first node within the conditional clock buffer circuit, the first circuit configured to generate a first state on the first node responsive to a first phase of the clock input;
- a second circuit coupled to receive the clock input and the condition signal and coupled to the first node, wherein the second circuit is configured to conditionally generate a second state on the first node during a condition window within a second phase of the clock input, wherein the condition window excludes at least a portion of the second phase, and wherein the second circuit is configured to conditionally generate the third state responsive to the condition signal during the condition window;
- and
- a third circuit coupled to the first node and to the clock output, the third circuit configured to generate a third state on the clock output responsive to the first state on the first node and configured to generate a fourth state on the clock output responsive to the second state on the first node.
Dependencies are inferred from the claim text.