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US 6,784,711 B2Granted
Sequential pulse train generator
AssigneeAu Optronics Corporation
InventorJian-Shen Yu
Life of this patent
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Abstract
A sequential pulse train generator. Each stage of the sequential pulse train generator includes a dynamic shift register circuit, level shifter, and buffer composed of inverters. The dynamic shift register circuits, allow the pulse generator to operate with a low-voltage clock signal so that power consumption in transmission of the clock signal is reduced.
Claims15
A sequential pulse train generator consists of thin-film transistors, comprising:
- a first and second dynamic shift register circuit, each of which has a first, second, third, fourth, and fifth input terminal, and a first and second output terminal, first, second, third and fourth input terminal of the first dynamic shift register circuit coupled to receive an initial pulse train, the inverted initial pulse train, a clock signal and the inverted clock signal, the fifth input terminal of the first dynamic shift register circuit coupled to the first input terminal of the second dynamic shift register circuit, the third and fourth input terminal of the second dynamic shift register circuit coupled to receive the inverted clock signal and the clock signal, respectively;
- a first and second level shifter, each of which has a first and second input terminal, and an output terminal, the first and second input terminal of the first level shifter coupled to the first and second output terminal of the first dynamic shift register circuit, the output terminal of the first level shifter coupled to the fifth output terminal of the first dynamic shift register circuit, the first and second input terminal of the second level shifter coupled to the first and second output terminal of the second dynamic shift register circuit, the output terminal of the second level shifter coupled to the fifth output terminal of the second dynamic shift register circuit, respectively;
- and
- a first and second inverter having output terminals coupled to the output terminals of the first and second level shifter, and outputting a first and second sequential pulse train, the output terminal of the first inverter coupled to the second input terminal of the second dynamic shift register circuit,
- wherein the amplitude of the clock signal is not larger than half the amplitude of the output signal of the inverter.
2 more elements
A sequential pulse train generator consists of thin-film transistors, comprising:
- a first, second and third dynamic shift register circuit, each of which has a first, second, third, and fourth input terminal, and a first and second output terminal, the first, second and third input terminal of the first dynamic shift register circuit coupled to receive an initial pulse train, the inverted initial pulse train and a clock signal, the fourth input terminal of the first dynamic shift register circuit coupled to the second input terminal of the third dynamic shift register circuit, the third input terminal of the second dynamic shift register circuit coupled to receive the inverted clock signal, the third input terminal of the third dynamic shift register circuit coupled to receive the clock signal;
- a first, second and third level shifter, each of which has a first and second input terminal, and an output terminal, the first and second input terminal of the first level shifter coupled to the first and second output terminal of the first dynamic shift register circuit, the first and second input terminal of the second level shifter coupled to the first and second output terminal of the second dynamic shift register circuit, the first and second input terminal of the third level shifter coupled to the first and second output terminal of the third dynamic shift register circuit;
- and
- a second, third, fourth, fifth, sixth and seventh inverter, input terminals of the second, third and fourth inverter coupled to the output terminals of the first, second and third level shifter, output terminals of the second and third inverter coupled to the first input terminals of the second and third dynamic shift register circuit, input terminals of the fifth, sixth and seventh inverter coupled to the output terminals of the second, third and fourth inverter, an output terminal of the fifth inverter coupled to the second input terminal of the second dynamic shift register circuit, the output terminals of the fifth, sixth and seventh inverter outputting a first, second and third sequential pulse train, respectively,
- wherein the amplitude of the clock signal is not larger than half the amplitude of the output signal of the inverter.
2 more elements
A sequential pulse train generator consists of thin-film transistors, comprising:
- a first, second and third dynamic shift register circuit, each of which has a first, second and third input terminal, and a first and second output terminal, the first and second input terminal of the first dynamic shift register circuit coupled to receive an initial pulse train and a clock signal, the third input terminal of the first dynamic shift register circuit coupled to the first input terminal of the third dynamic shift register circuit, the second input terminal of the second dynamic shift register circuit coupled to receive the inverted clock signal, the second input terminal of the third dynamic shift register circuit coupled to receive the clock signal;
- a first, second and third level shifter, each of which has a first and second input terminal, and an output terminal, the first and second input terminal of the first level shifter coupled to the first and second output terminal of the first dynamic shift register circuit, the first and second input terminal of the second level shifter coupled to the first and second output terminal of the second dynamic shift register circuit, the first and second input terminal of the third level shifter coupled to the first and second output terminal of the third dynamic shift register circuit;
- and
- a first, second and third buffer, input terminals of the first, second and third buffer coupled to the output terminals of the first, second and third level shifter, output terminals of the second buffer coupled to the third input terminal of the first dynamic shift register circuit and to the first input terminal of the third dynamic shift register circuit;
- wherein the amplitude of the clock signal is not larger than half the amplitude of the output signal of the inverter.
2 more elements
Dependencies are inferred from the claim text.