Clock generator to control a pules width according to input voltage level in semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorJe-Hun Ryu
Life of this patent
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Abstract
A clock generator to produce internal clock signals with a controlled pulse width in a synchronous semiconductor memory device. The clock generator includes a clock input circuit receiving an external clock signal, a reference voltage signal and an option signal, and outputting first and second clock signals; a clock driver receiving the first clock signal and outputting an internal clock signal in response to the option signal; and a detector receiving the second clock signal and outputting the option signal in response to a control signal.
Claims17
A clock generating circuit in a semiconductor device comprising:
- clock input means for receiving an external clock signal, a reference voltage signal and an option signal, and for outputting first and second clock signals;
- clock driving means for receiving the first clock signal from the clock input means and for outputting an internal clock signal in response to the option signal;
- and
- a detecting means for receiving the second clock signal from the clock input means and for outputting the option signal to maintain a pulse width of the internal clock signal at a stable value without much fluctuation to the clock input means and the clock driving means in response to a control signal.
A clock generating circuit in a semiconductor device comprising:
- clock input means for receiving an external clock signal, a reference voltage signal and an option signal, and for outputting first and second clock signals;
- clock driving means for receiving the first clock signal from the clock input means and for outputting an internal clock signal in response to the option signal;
- a detecting means for receiving the second clock signal from the clock input means and for outputting the option signal to maintain a pulse width of the internal clock signal at a stable value without much fluctuation to the clock input means and the clock driving means in response to a control signal;
- and
- means for outputting the control signal to determine operation of the clock generating circuit in response to command signal from a system controller.
A clock generating circuit in a semiconductor device comprising:
- clock input means for receiving an external clock signal, a reference voltage signal and an option signal, and for outputting first and second clock signals;
- clock driving means for receiving the first clock signal and outputting an internal clock signal in response to the option signal;
- a mode register outputting the control signal in response to a command signal from a system controller;
- and
- means for producing the option signal to maintain a pulse width of the internal clock signal at a stable value without much fluctuation.
Dependencies are inferred from the claim text.