Method of stabilizing phase-locked loop

A phase-locked loop comprising:

• a controlled oscillator for generating an output signal;
• a phase detector for detecting difference in phase between a feedback signal and a reference signal;
• an integrator including a first register for storing a frequency setting for said controlled oscillator and a second register;
• and
• a controller for transferring the contents of said first register to said second register during normal operation so that after a phase or frequency jump the contents of said first register prior to said jump can be restored when a phase hit occurs so as to restore the frequency setting of the controlled oscillator prior to the phase or frequency jump;
• wherein said integrator further comprises a multiplexer having a first input receiving an output value from said phase detector, a second input connected to an input of said controlled oscillator, a third input receiving the output value of said second register, and an output connected to respective inputs of said first and second registers so that said first and second registers are loaded in parallel;
• and
• wherein said controller selects the input of said multiplexer connected to the output of said second the second register after a phase hit following a phase or frequency jump to restore the contents of said first register.

A method of rapidly bringing a phase-locked loop subject to overshoot into lock after phase or frequency jump, said phase-locked loop having a phase detector, a controlled oscillator, and an integrator having an output frequency setting that, with the output of said phase detector, determines a frequency setting of said controlled oscillator, said method comprising the steps of:

• storing a value for the output frequency setting of said integrator in a first register prior to said phase or frequency jump;
• transferring the contents of said first register to said second register;
• providing a multiplexer having a first input connected to an output of said phase detector, a second input connected to an output of said second register, and an output connected to an input of said first register;
• selecting said first input during normal operation;
• determining when a phase hit occurs after said phase or frequency jump;
• and
• restoring the output frequency setting of said integrator to said stored value on or soon after said phase hit to reduce overshoot by selecting said second input of said multiplexer.