Dynamic driver boost circuits
AssigneeInternational Business Machines Corporation
InventorsJason Chung, Hongfei Wu, Songtao Xu
Life of this patent
Estimating the term…
Abstract
In order to reduce slew rate and minimize delay skew, the invention adds a pull-down booster circuit connected to the gate of the driving transistor and/or a pull-up booster circuit connected the gate of the driving transistor. The pull-down booster circuit is adapted to dynamically pull-down the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from a first voltage (e.g., a logical “0”) to a second voltage (e.g., a logical “1”). The pull-up booster circuit is adapted to dynamically pull-up the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from the second voltage to the first voltage.
Claims38
A driver circuit comprising:
- a logical enable device having an input and an output;
- a driving transistor having a gate connected to said output of said logical enable device;
- and at least one of:
- a pull-down booster circuit connected to said gate of said driving transistor, wherein said pull-down booster circuit is adapted to dynamically pull-down a voltage at said gate of said driving transistor when a voltage level at said input to said logical enable device changes from a first voltage to a second voltage;
- and
- a pull-up booster circuit connected said gate of said driving transistor, wherein said pull-up booster circuit is adapted to dynamically pull-up a voltage at said gate of said driving transistor when a voltage level at said input to said logical enable device changes from said second voltage to said first voltage.
A driver circuit comprising:
- a logical enable device;
- a driving transistor having a gate connected to an output of said logical enable device;
- and
- a pull-down booster circuit comprising:
- a logical NAND device having first and second inputs, wherein said first input is connected to an input signal supplied to said logical enable device;
- and
- a pull-down transistor having a gate connected to an output of said NAND device, a source connected to said gate of said driving transistor, and a drain connected to ground,
- wherein said second input of said logical NAND device is connected to said gate of said driving transistor, such that said logical NAND device dynamically activates said pull-down transistor to pull-down said gate of said driving transistor to ground only while said input signal and said gate of said driving transistor are at the same logic level.
A driver circuit comprising:
- a logical enable device;
- a driving transistor having a gate connected to an output of said logical enable device;
- and
- a pull-up booster circuit comprising:
- a logical NOR device having first and second inputs, wherein said first input is connected to an input signal supplied to said logical enable device;
- and
- a pull-up transistor having a gate connected to an output of said NOR device, a drain connected to said gate of said driving transistor, and a source connected to a first voltage level,
- wherein said second input of said logical NOR device is connected to said gate of said driving transistor, such that said logical NOR device activates said pull-up transistor to pull-up said gate of said driving transistor to said first voltage level only while said input signal supplied to said logical enable and said gate of said driving transistor are at the same logic level.
A driver circuit comprising:
- a logical enable device;
- a driving transistor having a gate connected to an output of said logical enable device;
- a pull-down booster circuit comprising:
- a logical NAND device having first and second inputs, wherein said first input is connected to an input signal supplied to said logical enable device;
- and
- a pull-down transistor having a gate connected to an output of said NAND device, a source connected to said gate of said driving transistor, and a drain connected to ground,
- wherein said second input of said logical NAND device is connected to said gate of said driving transistor, such that said logical NAND device dynamically activates said pull-down transistor to pull-down said gate of said driving transistor to ground only while said input signal and said gate of said driving transistor are both at a first logic level;
- and
- a pull-up booster circuit comprising:
- a logical NOR device having first and second inputs, wherein said first input is connected to an input signal supplied to said logical enable device;
- and
- a pull-up transistor having a gate connected to an output of said NOR device, a drain connected to said gate of said driving transistor, and a source connected to a first voltage level,
- wherein said second input of said logical NOR device is connected to said gate of said driving transistor, such that said logical NOR device activates said pull-up transistor to pull-up said gate of said driving transistor to said first voltage level only while said input signal supplied to said logical enable and said gate of said driving transistor are both at a second logic level.
A pull-down booster circuit for use with a driver having a logical enable device, said pull-down booster circuit comprising:
- a logical NAND device having first and second inputs, wherein said first input is connected to an input signal supplied to said logical enable device;
- and
- a transistor having a gate connected to an output of said NAND device, a source connected to an output of said logical enable device, and a drain connected to ground,
- wherein said second input of said logical NAND device is connected to said output of said logical enable device, such that said logical NAND device dynamically activates said transistor to pull-down said output of said logical enable device to ground only while said input signal and a signal on said output of said logical enable device are at the same logic level.
A pull-up booster circuit for use with a driver having a logical enable device, said pull-up booster circuit comprising:
- a logical NOR device having first and second inputs, wherein said first input is connected to an input signal supplied to said logical enable device;
- and
- a transistor having a gate connected to an output of said NOR device, a drain connected to an output of said logical enable device, and a source connected to a first voltage level,
- wherein said second input of said logical NOR device is connected to said output of said logical enable device, such that said logical NOR device activates said transistor to pull-up said output of said logical enable device to said first voltage level only while said input signal supplied to said logical enable device and a signal on said output of said logical enable device at are at the same logic level.
Dependencies are inferred from the claim text.