CMOS buffer circuit

A CMOS buffer circuit comprising:

• a first CMOS inverter for inverting an input digital signal and for outputting the resultant signal as a first inverted signal;
• a second CMOS inverter for inverting said first inverted signal and for outputting the resultant signal as a second inverted signal;
• and
• a delay circuit, having a transmission delay time that becomes longer as the temperature rises, for outputting to said second inverter, following a delay equivalent to the transmission delay time, said first inverted signal received from said first inverter,
• wherein said first CMOS inverter includes
• a first p-channel MOSFET, which has a first threshold value that becomes smaller as the temperature rises and which is rendered ON when a digital signal exceeds said first threshold value, and
• a first n-channel MOSFET, having a second threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to said first p-channel MOSFET, when a digital signal exceeds said second threshold value, and
• wherein said second CMOS inverter includes
• a second p-channel MOSFET, which has a third threshold value that becomes smaller as the temperature rises and which is rendered ON when said first inverted signal exceeds said third threshold value, and
• a second n-channel MOSFET, having a fourth threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to said second p-channel MOSFET, when said first inverted signal exceeds said fourth threshold value.