Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time

A clock multiplexer comprising:

• a first cascaded synchronization circuit configured to generate a first output clock in response to a reference clock and a switch control signal, said first cascaded synchronization circuit including a first cascaded flip-flop circuit generating an output signal in response to said switch control signal and said reference clock, a second cascaded flip-flop circuit-generating an output signal in response to the output of said first cascaded flip-flop circuit and a fast clock, a first combinational element generating an output signal in response to the output signals of said first and second cascaded flip-flop circuits, a third cascaded flip-flop circuit generating an output signal in response to the output signal of said first combinational element and said reference dock, a second combinational element generating said first output clock in response to the cutout signals of said first and third cascade flip-flop circuits and said reference clock;
• a second cascaded synchronization circuit configured to generate a second output clock in response to said fast clock and the switch control signal, said second cascaded synchronization circuit including a fourth cascaded flip-flop circuit generating an output signal in response to said switch control signal and said fast clock, a fifth cascaded flip-flop circuit generating an output signal in response to the output of said fourth cascaded flip-flop circuit and said reference clock, a third combinational element generating an output signal in response to the output signals of said fourth and fifth cascaded flip-flop circuits, a sixth cascaded flip-flop circuit generating an output signal in response to the cutout signal of said third combinational element and said fast clock, a fourth combinational element generating said second output clock in response to the output signals of said fourth and sixth cascaded flip-flop circuits and said fast clock;
• and
• a fifth combinational element configured to generate a substantially glitchless output clock in response to the first output clock and the second output clock.