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US 6,784,697 B2Granted
Method for clock control of clocked half-rail differential logic with sense amplifier and shut-off
AssigneeSun Microsystems, Inc.
InventorSwee Yew Choe
Life of this patent
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Abstract
Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or “dip” experienced by prior art half-rail differential logic circuits and is therefore more power efficient.
Claims22
A method for clock control of a cascaded chain of clocked half-rail differential logic circuits with sense amplifier and shut-off comprising:
- providing a first clocked half-rail differential logic circuit with sense amplifier and shut-off, said first clocked half-rail differential logic circuit with sense amplifier and shut-off comprising:
- a first clocked half-rail differential logic circuit with sense amplifier and shut-off first clock in terminal;
- a first clocked half-rail differential logic circuit with sense amplifier and shut-off second clock in terminal;
- at least one first clocked half-rail differential logic circuit with sense amplifier and shut-off data in terminal;
- and
- at least one first clocked half-rail differential logic circuit with sense amplifier and shut-off data out terminal;
- providing a second clocked half-rail differential logic circuit with sense amplifier and shut-off, said second clocked half-rail differential logic circuit with sense amplifier and shut-off comprising:
- a second clocked half-rail differential logic circuit with sense amplifier and shut-off first clock in terminal;
- a second clocked half-rail differential logic circuit with sense amplifier and shut-off second clock in terminal;
- at least one second clocked half-rail differential logic circuit with sense amplifier and shut-off data in terminal;
- and
- at least one second clocked half-rail differential logic circuit with sense amplifier and shut-off data out terminal;
- operatively coupling a first clock signal to said first clocked half-rail differential logic circuit with sense amplifier and shut-off first clock in terminal;
- operatively coupling a second clock signal to said second clocked half-rail differential logic circuit with sense amplifier and shut-off first clock in terminal;
- operatively coupling said second clock signal to said first clocked half-rail differential logic circuit with sense amplifier and shut-off second clock in terminal;
- operatively coupling said at least one first clocked half-rail differential logic circuit with sense amplifier and shut-off data out terminal to said at least one second clocked half-rail differential logic circuit with sense amplifier and shut-off data in terminal;
- and
- delaying said second clock signal with respect to said first clock signal by a predetermined delay time.
15 more elements
A method for clock control of a cascaded chain of clocked half-rail differential logic circuits with sense amplifier and shut-off comprising:
- providing a first supply voltage;
- providing a second supply voltage;
- providing a first clocked half-rail differential logic circuit with sense amplifier and shut-off, said first clocked half-rail differential logic circuit with sense amplifier and shut-off comprising:
- a first clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal;
- a first clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal;
- a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first supply voltage being coupled to said first transistor first flow electrode;
- a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said first transistor second flow electrode being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal;
- a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor second flow electrode being coupled to said third transistor first flow electrode, said third transistor second flow electrode being coupled to said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal;
- a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode, said second transistor control electrode being coupled to said fourth transistor first flow electrode and said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal, said third transistor control electrode being coupled to said fourth transistor second flow electrode and said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal;
- a logic network, said logic network comprising a logic network first IN terminal, a logic network second IN terminal, a logic network OUT terminal, a logic network OUTBAR terminal and a logic network fifth terminal;
- a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode, said fifth transistor first flow electrode being coupled to said logic network fifth terminal, said fifth transistor second flow electrode being coupled to said second supply voltage, said fifth transistor control electrode being coupled to a first clock signal;
- a first clocked half-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit coupled between said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal and said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal, said first clocked half-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit having an IN terminal coupled to a second clock signal;
- a first clocked half-rail differential logic circuit with sense amplifier and shut-off shut-off device coupled between said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal and said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal, said logic network OUT terminal being coupled to said first clocked half-rail differential logic circuit with sense amplifier and shut-off shut-off device and said logic network OUTBAR terminal being coupled to said first clocked half-rail differential logic circuit with sense amplifier and shut-off shut-off device;
- providing a second clocked half-rail differential logic circuit with sense amplifier and shut-off, said second clocked half-rail differential logic circuit with sense amplifier and shut-off comprising:
- a second clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal;
- a second clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal;
- a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first supply voltage being coupled to said first transistor first flow electrode;
- a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said first transistor second flow electrode being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal;
- a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor second flow electrode being coupled to said third transistor first flow electrode, said third transistor second flow electrode being coupled to said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal;
- a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode, said second transistor control electrode being coupled to said fourth transistor first flow electrode and said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal, said third transistor control electrode being coupled to said fourth transistor second flow electrode and said first clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal;
- a logic network, said logic network comprising a logic network first IN terminal, a logic network second IN terminal, a logic network OUT terminal, a logic network OUTBAR terminal and a logic network fifth terminal;
- a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode, said fifth transistor first flow electrode being coupled to said logic network fifth terminal, said fifth transistor second flow electrode being coupled to said second supply voltage;
- a second clocked half-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit coupled between said second clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal and said second clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal, said second clocked half-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit having an IN terminal coupled to a third clock signal,
- a second clocked half-rail differential logic circuit with sense amplifier and shut-off shut-off device coupled between said second clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal and said second clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal, said logic network OUT terminal being coupled to said first clocked half-rail differential logic circuit with sense amplifier and shut-off shut-off device and said logic network OUTBAR terminal being coupled to said second clocked half-rail differential logic circuit with sense amplifier and shut-off shut-off device;
- delaying said second clock signal with respect to said first clock signal by a predetermined delay time;
- and
- delaying said third clock signal with respect to said second clock signal by a predetermined delay time.
24 more elements
A method for clock control of a clocked half-rail differential logic circuit with sense amplifier and shut-off comprising:
- providing a first supply voltage;
- providing a second supply voltage;
- providing a clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal;
- providing a clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal;
- providing a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode;
- operatively coupling said first supply voltage to said first transistor first flow electrode;
- providing a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode;
- operatively coupling said first transistor second flow electrode to said second transistor first flow electrode;
- operatively coupling said second transistor second flow electrode to said clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal;
- providing a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode;
- operatively coupling said first transistor second flow electrode to said third transistor first flow electrode;
- operatively coupling said third transistor second flow electrode to said clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal;
- providing a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode;
- operatively coupling said second transistor control electrode to said fourth transistor first flow electrode;
- operatively coupling said second transistor control electrode to said clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal;
- operatively coupling said third transistor control electrode to said fourth transistor second flow electrode;
- operatively coupling said third transistor control electrode to said clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal;
- providing a logic network, said logic network comprising a logic network first IN terminal, a logic network second IN terminal, a logic network OUT terminal, a logic network OUTBAR terminal and a logic network fifth terminal;
- providing a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode;
- operatively coupling said fifth transistor first flow electrode to said logic network fifth terminal;
- operatively coupling said fifth transistor second flow electrode to said second supply voltage;
- operatively coupling said fifth transistor control electrode to a first clock signal;
- operatively coupling a clocked half-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit between said clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal and said clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal, said clocked half-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit having an IN terminal;
- operatively coupling said clocked half-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit IN terminal to a second clock signal;
- operatively coupling a clocked half-rail differential logic circuit with sense amplifier and shut-off shut-off device between said clocked half-rail differential logic circuit with sense amplifier and shut-off OUT terminal and said clocked half-rail differential logic circuit with sense amplifier and shut-off OUTBAR terminal;
- operatively coupling said logic network OUT terminal to said clocked half-rail differential logic circuit with sense amplifier and shut-off shut-off device
- operatively coupling said logic network OUT terminal and said logic network OUTBAR terminal to said clocked half-rail differential logic circuit with sense amplifier and shut-off shut-off device;
- and
- delaying said second clock signal with respect to said first clock signal by a predetermined time.
26 more elements
Dependencies are inferred from the claim text.