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US 6,784,695 B1Granted
Domino circuit topology
AssigneeIntel Corporation
InventorsHans L. Yeager, Scott E. Siers, Brian T. Ormson
Life of this patent
Estimating the term…
Abstract
A domino circuit topology that includes a dynamic circuit, logic circuit, and static circuit. The domino circuit includes a dynamic circuit, logic circuit, and static circuit coupled through a central node. The dynamic circuit includes a pre-charge circuit and a keeper circuit for pre-charging the central node and keeping the central node at its current voltage level. The static circuit provides a static output for the domino circuit. The logic circuit provides logical functions for input signals. In addition, the domino circuit can include an isolation transistor coupled between the central node and the logic circuit.
Claims24
A circuit, comprising:
- a dynamic circuit that pre-charges a node;
- a plurality of logic circuits coupled to the dynamic circuit through the node, the plurality of logic circuits to perform a logic operation;
- and
- a plurality of isolation transistors coupled between the plurality of logic circuits and the node.
1 more element
A circuit, comprising:
- a dynamic circuit that pre-charges a node;
- a logic circuit coupled to the dynamic circuit through the node, the logic circuit to perform a logic operation;
- and
- a transistor coupled between the logic circuit and the node, wherein the logic circuit further comprises:
- a first plurality of transistors, each of the first plurality of transistors having a gate connected to a first input and a drain connected to the transistor;
- and
- a second plurality of transistors, each of the second plurality of transistors having a gate connected to a second input, a source connected to a reference voltage, and a drain connected to a source of one of the first plurality of transistors.
4 more elements
A system comprising:
- a die comprising a microprocessor;
- and
- an off-die component in communication with the microprocessor;
- wherein the microprocessor comprises:
- a dynamic circuit that pre-charges a node;
- a logic circuit coupled to the dynamic circuit through the node, the logic circuit performs a logic operation;
- a transistor coupled between the logic circuit and the node;
- and
- a static circuit coupled to the node and an output, the static circuit holds the output in a static state, wherein the logic circuit further comprises:
- a first plurality of transistors, each of the first plurality of transistors having a gate connected to a first input and a drain connected to the transistor;
- and
- a second plurality of transistors, each of the second plurality of transistors having a gate connected to a second input, a source connected to a reference voltage, and a drain connected to a source of one of the first plurality of transistors.
9 more elements
A domino circuit topology, comprising:
- a plurality of logic circuits that perform a logic operation;
- a plurality of isolation transistors each coupled between a node and a respective one of the plurality of logic circuits;
- a first transistor coupled between a first voltage source and the node, the first transistor coupling the first voltage source to the node during a first phase;
- a second transistor coupled between the first voltage source and the node, the second transistor coupling the first voltage source to the node during a second phase;
- and
- a third transistor coupled between the plurality of logic circuits and the node, the third transistor coupling the plurality of logic circuits to the node during the second phase.
3 more elements
A domino circuit topology, comprising:
- a logic circuit that performs a logic operation;
- a first transistor coupled between a first voltage source and a node, the first transistor coupling the first voltage source to the node during a first phase;
- a second transistor coupled between the first voltage source and the node, the second transistor coupling the first voltage source to the node during a second phase;
- and
- a third transistor coupled between the logic circuit and the node, the third transistor coupling the logic circuit to the node during the second phase, wherein the logic circuit further comprises:
- a first plurality of transistors, each of the first plurality of transistors having a gate connected to a first input and a drain connected to the third transistor;
- and
- a second plurality of transistors, each of the second plurality of transistors having a gate connected to a second input, a source connected to a reference voltage source, and a drain connected to a source of one of the first plurality of transistors.
5 more elements
Dependencies are inferred from the claim text.