CMOS sequential logic configuration for an edge triggered flip-flop

An CMOS sequential logic configuration for an edge triggered flip-flop, comprising:

• at least one PMOS transistor and a plurality of NMOS transistors matched and joined as a plurality of separate gate inputs and including an output, a first node, and a second node, wherein the first and second nodes define an internal voltage between one or more input transistors and one or more output transistors;
• a first latch connected to the first node;
• and
• a second latch connected to the second node, wherein the first and second latches are connected to separate reference voltage sources to prevent a floating voltage state for each of the first and second nodes.

A method of producing a circuit output signal in an CMOS flip-flop circuit in response to one or more edges of a clock input signal, comprising:

• generating an input signal to an PMOS transistor and an NMOS transistor having a plurality of transistors connected therebetween;
• providing a clock signal to at least one of the plurality of transistors;
• generating a first node signal from the PMOS transistor to a first latch and a second node signal from the NMOS transistor to a second latch, the first and second latches configured to prevent a floating voltage state for each of the first and second node signals;
• and
• wherein the first and second node signals generate the circuit output signal.

An CMOS cascaded circuit, comprising:

• means for generating a clock signal;
• means for delaying the clock signal to one or more clock input transistors;
• means for receiving an inverted input, the means for receiving an inverted input having a first node output;
• means for receiving an input, the means for receiving an input having a second node output;
• and
• means for controlling voltage levels of the first and second node outputs to generate a circuit output signal.