FPGA with improved structure for implementing large multiplexers
AssigneeXilinx, Inc.
InventorAlireza S. Kaviani
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Abstract
Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.
Claims12
A multiplexing input structure in a field programmable gate array (FPGA), the FPGA comprising a general interconnect structure and a plurality of configurable logic blocks (CLBs), the multiplexing input structure comprising:
- a first plurality of data input terminals coupled to the general interconnect structure;
- a first bypass input terminal coupled to the general interconnect structure;
- a first multiplexing output terminal coupled to a function generator input terminal of one of the CLBs;
- and
- a first multiplexing circuit having a second plurality of data input terminals coupled to the first plurality of data input terminals, a first select terminal coupled to the first bypass input terminal, and an output terminal coupled to the multiplexing output terminal.
Dependencies are inferred from the claim text.