Circuit and method for dynamically controlling the impedance of an input/output driver

An input/output (IO) device comprising:

• a power supply node;
• an input node for receiving an input data signal;
• an output node for outputting an output data signal generated in response to the input node receiving the input data bit signal;
• a pull-up driver coupled to the power supply node and the output node;
• a circuit coupled to the input node, the pull-up driver, and the output node, wherein the circuit is configured to generate a signal that is provided to the pull-up driver, wherein the signal to the pull-up driver varies as a function of the voltage at the output node and the voltage of the input data signal;
• and
• wherein the circuit comprises first, second, and third p-channel FETs and a p-channel FET, wherein the source and drain of the first and second n-channel FETs are coupled together, the sources of the second n-channel FET and the p-channel FET are coupled together, the drains of the p-channel FET and the third n-channel FET are coupled together and to the pull-up driver, the source of the third n-channel FET is coupled to the input node, the gates of the first and third n-channel FETs are coupled to an n-channel bias voltage node, the gate of the second n-channel device is coupled to the output node, and the gate of the p-channel FET is coupled to a p-channel bias voltage node.

An apparatus comprising:

• a microprocessor;
• a memory device;
• a data bus coupled between the microprocessor and the memory device;
• wherein the processor comprises and IO device, the IO device comprising:
• a power supply node;
• an input node for receiving an input data signal;
• an output node for outputting an output data signal generated in response to the input node receiving the input data bit signal;
• a pull-up driver coupled to the power supply node and the output node;
• a circuit coupled to the input node, the pull-up driver, and the output node, wherein the circuit is configured to generate a signal that is provided to the pull-up driver,
• wherein the signal provided to the pull-up driver varies as a function of the voltage at the output node and the voltage of the input data signal;
• and
• wherein the pull-un driver comprises first and second p-channel field effect transistors (FETs), wherein the drain of the first p-channel FET is coupled to the source of the second p-channel FET, the source of the first p-channel FET is coupled to the power supply node, the drain of the second p-channel FET is coupled to the output node, the gate of the first p-channel FET is coupled to receive the signal generated by the circuit, and the gate of the second p-channel FET is coupled to a p-channel bias voltage node.

An apparatus comprising:

• a microprocessor;
• a memory device;
• a data bus coupled between the microprocessor and the memory device;
• wherein the processor comprises and IO device, the IO device comprising:
• a power supply node;
• an input node for receiving an input data signal;
• an output node for outputting an output data signal generated in response to the input node receiving the input data signal;
• a pull-up driver coupled to the power supply node and the output node;
• a circuit coupled to the input node, the pull-up driver, and the output node, wherein the circuit is configured to generate a signal that is provided to the pull-up driver,
• wherein the signal provided to the pull-up driver varies as a function of the voltage at the output node;
• and
• wherein the circuit comprises first, second, and third n-channel FETs and a p-channel FET, wherein the source and drain of the first and second n-channel FETs are coupled together, the sources of the second n-channel FET and the p-channel FET are coupled together, the drains of the p-channel FET and the third n-channel FET are coupled together and to the pull-up driver, the source of the third n-channel FET is coupled to the input node, the gates of the first and third n-channel FETs are coupled to an n-channel bias voltage node, the gate of the second n-channel device is couple do the output node, and the gate of the p-channel FET is coupled to a p-channel bias voltage node.

An input/out (IO) device comprising:

• a power supply node;
• an input for receiving an input data signal;
• an output for outputting an output data signal generated in response to the input node receiving the input data bit signal;
• a pull-up driver including an input to receive a signal that varies as a function of the voltage at the output node and the voltage of the input data signal, the pull-up driver coupled to the power supply node and the output node;
• wherein the pull-up driver comprises an impedance at the output node which is constant for all voltages at the output node.