Semiconductor integrated circuit testing system and method

A semiconductor integrated circuit testing method using a testing system including a wafer tray for holding a semiconductor wafer on which a plurality of semiconductor integrated circuit devices respectively having external electrodes are formed;

• an interconnect substrate having interconnect layers to which a testing voltage is externally input;
• a ring-shaped sealing member provided between said wafer tray and said interconnect substrate for forming a sealed space together with said wafer tray and said interconnect substrate;
• an elastic sheet held on said interconnect substrate at a periphery thereof;
• a plurality of probe terminals provided on said elastic sheet in positions respectively corresponding to said external electrodes of said plurality of semiconductor integrated circuit devices and electrically connected to said interconnect layers;
• and a plurality of protrusions protruding toward said wafer tray and provided on said elastic sheet, said external electrodes and said interconnect layers are not electrically connected to each other via each of said plurality of protrusions,
• the method comprising the steps of:
• holding said semiconductor wafer on said wafer tray with said external electrodes of said plurality of semiconductor integrated circuit devices respectively facing said plurality of probe terminals provided on said elastic sheet;
• forming said sealed space with said wafer tray, said ring-shaped sealing member and said interconnect substrate by making said wafer tray holding said semiconductor wafer and said interconnect substrate come close to each other;
• reducing an internal pressure of said sealed space for bringing said plurality of probe terminals into contact with said external electrodes respectively facing said plurality of probe terminals;
• and
• testing electric characteristics of said plurality of semiconductor integrated circuit devices in the lump by applying the testing voltage to said external electrodes in contact with said plurality of probe terminals through said interconnect layers and said plurality of probe terminals,
• wherein the step of reducing the internal pressure of said sealed space includes a sub-step of preventing said interconnect substrate from deforming toward said wafer tray by bringing said plurality of protrusions into contact with said semiconductor wafer held on said wafer tray.

A semiconductor integrated circuit testing system for testing electric characteristics of a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer in the lump, comprising:

• a wafer tray for holding said semiconductor wafer;
• an interconnect substrate facing said semiconductor wafer held by said wafer tray and having interconnect layers to which a testing voltage is externally input;
• a ring-shaped sealing member provided between said wafer tray and said interconnect substrate for forming a sealed space together with said wafer tray and said interconnect substrate;
• an elastic sheet held on said interconnect substrate at a periphery thereof;
• a plurality of probe terminals provided on said elastic sheet in positions respectively corresponding to external electrodes of said plurality of semiconductor integrated circuit devices and electrically connected to said interconnect layers;
• a plurality of protrusions protruding toward said wafer tray and provided on said elastic sheet, such that said external electrodes and said interconnect layers are not electrically connected to each other via each of said plurality of protrusions, and
• said plurality of protrusions is in contact with said interconnect layers when an internal pressure of said sealed space is reduced.

A semiconductor integrated circuit testing method using a testing system including a wafer tray for holding a semiconductor wafer on which a plurality of semiconductor integrated circuit devices respectively having external electrodes are formed;

• an interconnect substrate having interconnect layers to which a testing voltage is externally input;
• a ring-shaped sealing member provided between said wafer tray and said interconnect substrate for forming a sealed space together with said wafer tray and said interconnect substrate;
• an elastic sheet held on said interconnect substrate at a periphery thereof;
• a plurality of probe terminals provided on said elastic sheet in positions respectively corresponding to said external electrodes of said plurality of semiconductor integrated circuit devices and electrically connected to said interconnect layers;
• and a plurality of protrusions protruding toward said wafer tray and provided on said elastic sheet, said external electrodes and said interconnect layers are not electrically connected to each other via each of said plurality of protrusions,
• the method comprising the steps of:
• holding said semiconductor wafer on said wafer tray with said external electrodes of said plurality of semiconductor integrated circuit devices respectively facing said plurality of probe terminals provided on said elastic sheet;
• forming said sealed space with said wafer tray, said ring-shaped sealing member and said interconnect substrate by making said wafer tray holding said semiconductor wafer and said interconnect substrate come close to each other;
• reducing an internal pressure of said sealed space for bringing said plurality of probe terminals into contact with said external electrodes respectively facing said plurality of probe terminals;
• and
• testing electric characteristics of said plurality of semiconductor integrated circuit devices in the lump by applying the testing voltage to said external electrodes in contact with said plurality of probe terminals through said interconnect layers and said plurality of probe terminals,
• wherein the step of reducing the internal pressure of said sealed space includes a sub-step of bringing said plurality of protrusions into contact with said semiconductor wafer held on said wafer tray.