US 6,784,678 B2 · Test apparatus for semiconductor circuit and method of testing semiconductor circuits

Abstract

A wafer test apparatus for bringing the contact areas of the integrated circuits to be tested into electrical connection with the test contacts as uniformly as possible and therefore with relatively low necessary contact pressures. The test apparatus has a chuck for holding a wafer having at least one integrated circuit with a group of contact areas which define a wafer surface profile. A test head is configured opposite the chuck and has a performance board, on which a probe card with contacts for making contact with the contact areas of the integrated circuit is configured. Areas of the contacts, of the probe card, which are intended to come into contact with the contact areas define a test surface profile. Actuators are configured on the probe card for aligning the test surface profile in parallel with the wafer surface profile and for changing the distance between the performance board and the contacts in a direction substantially orthogonal to the wafer surface profile.

Claims26

Dependent claims

A test apparatus for testing at least one semiconductor integrated circuit having a group of contact areas defining a wafer surface profile, the test apparatus comprising:

a chuck for holding a wafer that has at least one semiconductor integrated circuit with a group of contact areas that define a wafer surface profile;
a test head that is configured opposite said chuck and that includes a performance board;
a probe card that is configured on said test head and that has contacts for making contact with the contact areas of the integrated circuit, said contacts having areas that are intended to come into contact with the contact areas of the integrated circuit and that define a test surface profile;
and
at least three actuators electrically driven to change actuator length according to an electrical signal from sensors, said at least three actuators being configured on said probe card for aligning the test surface profile parallel with the wafer surface profile prior to the test surface profile contacting the wafer surface profile, said actuators also changing a distance between said performance board and said contacts of said probe card in a direction substantially orthogonal to the wafer surface profile.

2 more elements

A method of testing semiconductor circuits in a test apparatus, which comprises:

providing a wafer that has at least one semiconductor integrated circuit with a group of contact areas that define a wafer surface profile;
providing a test apparatus that includes a chuck for holding the wafer;
providing the test apparatus with a test head that is configured opposite the chuck and that includes a performance board;
providing the test apparatus with a probe card that is configured on the test head and that has contacts for making contact with the contact areas of the integrated circuit;
providing the contacts on the probe card with areas that are intended to come into contact with the contact areas of the integrated circuit and that define a test surface profile;
providing the probe card with at least three actuators to change actuator length according to an electrical signal from the sensors;
using the at least three actuators to align the test surface profile parallel with the wafer surface profile prior to the test surface profiles contacting the wafer surface profile;
and
using the at least three actuators to enlarge a distance between the performance board and the contacts in a direction substantially orthogonal to the wafer surface profile until the contacts of the probe card have produced an electrical connection with the contact areas of the wafer.

6 more elements

Dependencies are inferred from the claim text.

Test apparatus for semiconductor circuit and method of testing semiconductor circuits

Life of this patent

Test apparatus for semiconductor circuit and method of testing semiconductor circuits

Life of this patent

Abstract

Claims26