Closed-grid bus architecture for wafer interconnect structure

An apparatus for providing a signal path between an integrated circuit tester channel and an array of input/output (I/O) pads on a semiconductor wafer, the apparatus comprising:

• a circuit board including a first circuit board layer and a second circuit board layer;
• an array of vias extending through at least one of said first and second circuit board layers having at least three rows and three columns of vias, each via corresponding to a separate one of said I/O pads, each row of vias including at least three vias, and each column of vias including at least three vias;
• first traces mounted on said first circuit board layer and extending in a first direction, one for each row of said vias, each first trace linking all vias of its corresponding row of vias;
• second traces mounted on said second circuit board layer and extending in a second direction, each second trace corresponding to a separate column of said vias and linking all vias of its corresponding column of vias, wherein said first and second traces and said vias form a closed-grid bus;
• first means for conductively linking said closed-grid bus to said tester channel;
• and
• second means for conductively linking each of said vias to its corresponding I/O pad.

A method for distributing a signal from a signal source to a plurality of destination nodes, the method comprising the steps of:

• a. providing an array of bus nodes having at least three rows and three columns of bus nodes, each bus node corresponding to a separate one of said plurality of destination nodes, each row of bus nodes including at least three bus nodes, and each column of said bus nodes including at least three bus nodes;
• b. providing a plurality of first daisy-chain buses, one for each of said rows of bus nodes, each first daisy-chain bus linking all bus nodes of a separate one of said rows of bus nodes, and each first daisy-chain bus having two ends;
• c. providing at least one second daisy-chain bus, each corresponding to a separate one of said columns of bus nodes and linking all bus nodes of the corresponding one of said columns of bus nodes;
• d. providing a plurality of conductors, each connected near said ends of said first daisy-chain buses, such that each first daisy-chain bus is linked to at least one other of said first daisy-chain buses, and such that said conductors and said first and second daisy-chain buses form a closed-grid bus conductively interconnecting all of said bus nodes of said array of bus nodes;
• e. conductively linking said closed-grid bus to said signal source;
• and
• f. conductively linking each of said bus nodes to its corresponding destination node.

A method for providing a signal path between an integrated circuit tester channel and an array of input/output (I/O) pads on a semiconductor wafer, the method comprising the steps of:

• a. providing a circuit board including a first substrate layer and a second substrate layer;
• b. forming an array of vias extending through at least one of said first and second substrate layers having at least three rows and three columns of vias, each via corresponding to a separate one of said I/O pads, each row of vias including at
• least three vias, and each column of vias including at least three vias;
• c. forming first traces on said first substrate layer extending in a first direction, one for each row of said vias, each first trace linking all vias of its corresponding row of vias;
• d. forming second traces on said second substrate layer extending in a second direction, each second trace corresponding to a separate column of said vias and linking all vias of its corresponding column of vias, wherein said first and second traces and said vias form a closed-grid bus;
• e. conductively linking said closed-grid bus to said tester channel;
• and
• f. conductively linking each of said vias to its corresponding I/O pad.