Semiconductor device inlcluding optimized driver layout for integrated circuit with staggered bond pads
AssigneeIntel Corporation
InventorMichael A. Jassowski
Life of this patent
Estimating the term…
Abstract
An embodiment of an integrated circuit die with staggered bond pads and optimized driver layout includes a staggered array of bond pads with an outer ring of bond pads and an inner ring of bond pads. Driver/ESD circuit cells for the outer ring of bond pads are located to the outside of the bond pads (between the outer ring of bond pads and the nearest die edge). The driver/ESD cells for the inner ring of bond pads are located to the inside of the bond pads (between the inner ring of bond pads and the die core). The integrated circuit die is coupled to a lead frame via bond wires.
Claims16
A semiconductor device, comprising:
- a die including
- a plurality of bond pads configured in an array,
- a first plurality of driver cells located between a nearest die edge and the plurality of bond pads, and
- a second plurality of driver cells located to the inside of the plurality of bond pads;
- and
- a lead frame including a plurality of lead fingers, the plurality of lead fingers coupled the plurality of bond pads by a plurality of bond wires.
A semiconductor device, comprising:
- a die including
- a plurality of bond pads configured in an array,
- a first plurality of driver cells located between a nearest die edge and the plurality of bond pads, and
- a second plurality of driver cells located to the inside of the plurality of bond pads;
- and
- a lead frame including a plurality of solder balls, the plurality of solder balls coupled the plurality of bond pads by a plurality of bond wires.
Dependencies are inferred from the claim text.