Semiconductor device having dummy patterns for metal CMP

A semiconductor device comprising:

• a semiconductor substrate;
• a MOS-structure transistor formed on a main surface of said semiconductor substrate, comprising a first main electrode region, a second main electrode region and a gate electrode for controlling currents flowing between said first main electrode region and said second main electrode region;
• an interlayer insulating film formed on an upper surface of said gate electrode, covering said MOS-structure transistor;
• and
• a metal dummy pattern formed on an upper surface of said interlayer insulating film and positioned above said upper surface of said gate electrode,
• wherein said first main electrode region is opposed to said second main electrode region in a first direction which corresponds to a direction of gate length of said gate electrode,
• said first main electrode region, said second main electrode region, said gate electrode and said metal dummy pattern extend in a second direction perpendicular to said first direction, which corresponds to a direction of gate width of said gate electrode, and
• a geometric center of said gate electrode in said second direction coincides with a geometric center of said metal dummy pattern in said second direction.