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US 6,784,533 B2Granted
Semiconductor device
AssigneeRenesas Technology Corp.
InventorsHiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
Life of this patent
Estimating the term…
Abstract
A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.
Claims16
A semiconductor device comprising:
- a semiconductor element comprising a plurality of pads including signal pads to input and output a signal, power pads to supply a power potential, and ground pads to supply a ground potential, all of which are formed on one main surface of said semiconductor element;
- and
- bump electrodes which are respectively connected with said signal pads by signal wiring sections, with said power pads by power wiring sections, and with said ground pads by ground wiring sections,
- wherein said pads include a first pad group comprising a ground pad, a power pad, and at least one pad connected to a data signal, a clock signal, a write-enable signal, or a data-mask signal, and a second pad group comprising a ground pad, a power pad, and at least one signal pad connected to an address signal, a clock enable signal, a column address strobe signal, or a row address strobe signal, and wherein ground and power pads in said first pad group are greater in number than the ground and power pads in said second pad group.
1 more element
A semiconductor device comprising:
- a plurality of terminal electrodes comprised of a first level conducting layer, each having a portion covered with a first level insulating layer and another portion exposed from said first level insulating layer;
- a second level conducting layer;
- a second level insulating layer formed over said second level conducting layer with a plurality of openings;
- and
- a plurality of bump electrodes formed in said openings and projected from the top surface of said second level insulating layer, said bump electrodes being electrically connected with said terminal electrodes corresponding to said bump electrodes via said second level conducting layer,
- wherein said terminal electrodes comprise a first pad group and a second pad group, said first pad group comprising a ground pad, a power pad, and at least one signal pad connected to a data signal, a clock signal, a write-enable signal, or a data-mask signal, and said second pad group comprising a ground pad, a power pad, and at least one signal pad connected to an address signal, a clock enable signal, a column address strobe signal, or a row address strobe signal, and wherein ground and power pads in said first pad group are greater in number than the ground and power pads in said second pad group.
3 more elements
A semiconductor device comprising:
- a semiconductor element comprising a plurality of pads including signal pads to input and output a signal, power pads to supply a power potential, and ground pads to supply a ground potential, all of which are formed on one main surface of said semiconductor element;
- bump electrodes which are respectively connected with said signal pads by signal wiring sections, with said power pads by power wiring sections, and with said ground pads by ground wiring sections;
- and
- wherein said pads are arranged in a sequence of a combination of one first signal pad, one ground pad, one second signal pad, and one power pad arranged in this order along a line.
1 more element
A semiconductor device including:
- a semiconductor element having external terminals located at a first level and external electrodes located on an organic insulator layer formed on said first level;
- wherein said external terminals comprise:
- power terminals for supplying a power potential, ground terminals for supplying a ground potential and signal terminals for at least one of inputting and outputting a signal, all of which are formed on one main surface of the semiconductor element;
- said external electrodes comprising power electrodes being connected with said power terminals via power wiring sections;
- and ground electrodes being connected with said ground terminals via ground wiring sections;
- wherein an external terminal sequence is comprised of a sequence of a combination of one first signal terminal, one ground terminal, one second signal terminal, and one power terminal located along a line.
3 more elements
A semiconductor device comprising:
- a semiconductor element comprising a pad terminal including signal pads to input and output a signal, power pads to supply a power potential, and ground pads to supply a ground potential, all of which are formed on one main surface of said semiconductor element;
- bump electrodes which are respectively connected with said signal pads by signal wiring sections, with said power pads by power wiring sections, and with said ground pads by ground wiring sections;
- and
- wherein said pad terminal is arranged to provide a sequence of a combination of one signal pad and one ground pad or one power pad located in this order along a line so that each signal pad is surrounded by either a pair of around pads or a pair of power pads immediately adjacent thereto.
1 more element
A semiconductor device comprising:
- a semiconductor element having external terminals located at a first level and external electrodes located at a second level higher than said first level;
- wherein said external terminals comprise:
- power terminals for supplying a power potential, ground terminals for supplying a ground potential and signal terminals for at least one of inputting and outputting a signal, all of which are formed on one main surface thereof;
- said external electrodes comprising:
- power electrodes being connected with said power terminals via power wiring sections;
- ground electrodes being connected with said ground terminals via ground wiring sections;
- and
- signal electrodes being connected with said signal terminals via signal wiring sections;
- wherein an external terminal sequence is comprised of a sequence of a combination of one signal terminal and one ground terminal or one power terminal located in this order along a line so that each signal terminal is surrounded by either a pair of ground terminals or a pair of power terminals immediately adjacent thereto.
6 more elements
A semiconductor device including:
- a semiconductor element having external terminals located at a first level and external electrodes located on an organic insulator layer formed on said first level;
- wherein said external terminals comprise:
- power terminals for supplying a power potential, ground terminals for supplying a ground potential and signal terminals for at least one of inputting and outputting a signal, all of which are formed on one main surface of said semiconductor element;
- said external electrodes comprising:
- power electrodes being connected with said power terminals via power wiring sections;
- and
- ground electrodes being connected with said ground terminals via ground wiring sections,
- wherein first power terminals or ground terminals are located on both sides of a first signal terminal, and second power terminals or ground terminals are located on both sides of a said second signal terminal.
5 more elements
A semiconductor device comprising:
- a semiconductor element having signal pads to input and output a signal, power pads to supply a power potential, and ground pads to supply a ground potential, all of which are formed on one main surface of said semiconductor element;
- and
- bump electrodes which are respectively connected with said signal pads by signal wiring sections, with said power pads by power wiring sections, and with said ground pads by ground wiring sections,
- wherein said pads comprising a first pad group and a second pad group, said first pad group comprising a ground pad, a power pad, and at least a data pad, and said second pad group comprising a ground pad, a power pad, and at least an address pad, and wherein said ground and power pads in said first pad group are greater in number than the number of ground and power pads in said second pad group.
1 more element
Dependencies are inferred from the claim text.