Three-dimensional memory array incorporating serial chain diode stack

A multi-level memory array comprising:

• on alternate levels of the memory array, a respective plurality of parallel spaced-apart conductors disposed above the substrate running in a first direction;
• on the other levels of the memory array, a respective plurality of parallel spaced-apart conductors disposed above the substrate and running in a second direction different than the first direction, such that a projection of the conductors on one level to the conductors on an adjacent level defines intersections therebetween;
• and
• a programmable layer of material separating the conductors on one level from the conductors on an adjacent level, the programmable layer of material at each intersection of conductors having a conductivity capable of being modified by application of a voltage and forming, at least before or after the application of the voltage, a steering device between successive levels of conductors;
• wherein the steering devices between successive levels of conductors are each oriented in a like direction.

A multi-level non-volatile memory array comprising:

• a plurality of first conductors disposed at a first and third level running generally in a first direction above a substrate;
• a plurality of second conductors disposed at a second and fourth level above the substrate and running in a second direction, and
• a plurality of dielectric regions each disposed respectively between successive levels of the first and second conductors which are capable of being selectively breached to form a diode between successive levels of the first and second conductors;
• wherein the resulting diodes between successive levels of the first and second conductors are each oriented in a like direction.

A multi-level non-volatile memory array comprising:

• a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate;
• a plurality of second rail-stacks disposed at a second and fourth level above the substrate and running in a second direction, and
• a plurality of dielectric regions each disposed respectively between successive levels of the first and second rail-stacks which are capable of being selectively breached to form a diode between successive levels of the first and second rail-stacks;
• wherein the resulting diodes between successive levels of the first and second rail-stacks are each oriented in a like direction.