Semiconductor integrated circuit device

A mass-produced solid state device comprising:

• a solid state material substrate having a top surface;
• and
• a defect-free solid state material layer no more than three atomic layers thick having at least one atomically smooth major surface, and positioned on the top surface of the substrate;
• at least a central portion of the solid state material layer having a non-flat major surface uniformly contacting intimately onto at least a selected portion of the top surface of the solid state material substrate to avoid production problems due to excessive leakage current, said solid state material substrate having a central portion of zero bottom width.

A mass-produced solid state device comprising:

• a solid state material substrate having a top surface;
• and
• a defect-free solid state material layer no more than three atomic layers thick having at least one atomically smooth major surface, and positioned on the top surface of the substrate;
• at least a central portion of the solid state material layer having a non-flat major surface uniformly contacting intimately onto at least a selected portion of the top surface of the solid state material substrate to avoid production problems due to excessive leakage current and including
• first and second solid state material substrate pockets positioned adjacent to each other, but laterally separated by a gap, on top surface of the substrate;
• the solid state material layer filling and bridging the gap between the two adjacent solid state material pockets;
• and
• at least a portion of the solid state material layer having an accuracy in thickness of better than two atomic layers;
• and in which:
• the first and second solid state material substrate pockets are respectively source and drain semiconductor pockets in a solid state device and separated by a gap from each other;
• the solid state material layer is an insulating gate layer filling and bridging the gap between the two pockets;
• and
• the gate layer material has an atomically smooth surface on at least one of the top and bottom major surfaces thereof.

A mass-produced solid state device comprising:

• a solid state material substrate having a top surface;
• a defect-free solid state material layer no more than three atomic layers thick having at least one atomically smooth major surface, and positioned on the top surface of the substrate;
• at least a central portion of the solid state material layer having a non-flat major surface uniformly contacting intimately onto at least a selected portion of the top surface of the solid state material substrate to avoid production problems due to excessive leakage current, and including
• first and second solid state material pockets positioned adjacent to each other, but laterally separated by a gap, on the top surface of the substrate;
• the solid state material layer filling and bridging the gap between the two adjacent solid state material pockets;
• and
• at least a portion of the solid state material layer having an accuracy in thickness of better than two atomic layers;
• and in which:
• each of a major portion of the substrate, solid state material pockets, and solid state material layer consists essentially of a single semiconductor material doped to no more than 10 ppm of impurities whereby the device is made resistant to dynamic forces due to impacts, vibrations, and large and rapid accelerations and decelerations.

A mass produced solid state device comprising:

• a solid state material substrate having a top surface;
• and
• a defect-free solid state material layer no more than three atomic layers thick having at least one atomically smooth major surface, and positioned on the top surface of the substrate;
• at least a central portion of the solid state material layer having a non-flat major surface uniformly contacting intimately onto at least a selected portion of the top surface of the solid state material substrate to avoid production problems due to excessive leakage current, and including
• first and second solid state material pockets positioned adjacent to each other, but laterally separated by a gap, on the top surface of the substrate;
• the solid state material layer filling and bridging the gap between the two adjacent solid state material pockets;
• and
• at least a portion of the solid state material layer having an accuracy in thickness of better than two atomic layers;
• and in which:
• the first and second solid state material pockets are respectively source and drain semiconductor pockets in a solid state device;
• and
• the solid state material layer is a single-material gate layer;
• and including:
• a conductive gate electrode of an electrically conducting material positioned on the gate layer to control flow of electronic carriers from the source to the drain.

A mass-produced solid state device comprising:

• a solid state material substrate having a top surface;
• and
• a defect-free solid state material layer no more than three atomic layers thick having at least one atomically smooth major surface, and positioned on the top surface of the substrate;
• at least a central portion of the solid state material layer having a non-flat major surface uniformly contacting intimately onto at least a selected portion of the top surface of the solid state material substrate to avoid production problems due to excessive leakage current, and including:
• first and second solid state material pockets positioned adjacent to each other, but laterally separated by a gap, on top surface of the substrate;
• the solid state material layer filling and bridging the gap between the two adjacent solid state material pockets;
• and
• at least a portion of the solid state material layer having an accuracy in thickness of better than two atomic layers;
• and in which:
• the first and second solid state material pockets are respectively source and drain semiconductor pockets in a solid state device;
• and
• the solid state material layer is a single material gate layer;
• and
• a conductive gate electrode of an electrically conducting material positioned on the gate layer to control flow of electronic carriers from the source to the drain;
• the gate layer material is atomically smooth on at least one of top and bottom major surfaces thereof to achieve an exceptionally smooth and detect-free surface;
• and
• material of the gate layer being purest at a bottom surface facing the substrate.

A mass-produced solid state device comprising:

• a solid state material substrate;
• at least a first solid state pocket positioned on a first selected top surface of the substrate;
• and
• a solid state material layer less then three atomic layers thick and having at least one atomically smooth but curved major surface which intimately contacts uniformly the first selected surface of the substrate onto a first specified portion of the at least one first solid state material pocket and in which:
• the solid state material layer is a single-material gate layer containing an ion-implanted substance selected from the group consisting of oxygen and nitrogen.

A solid state material substrate having a top surface;

• and
• a defect-free solid state material layer no more than three atomic layers thick having at least one atomically smooth major surface, and positioned on the top surface of the substrate;
• at least a central portion of the solid state material layer having a non-flat major surface uniformly contacting intimately onto at least a selected portion of the top surface of the solid state material substrate to avoid production problems due to excessive leakage current, and including
• first and second solid state material pockets positioned adjacent to each other, but laterally separated by a gap, on the top surface of the substrate;
• the solid state material layer filling and bridging the gap between the two adjacent solid state material pockets;
• and
• at least a portion of the solid state material layer having an accuracy in thickness of better than two atomic layers;
• and in which:
• at least a part of the substrate is a semi conductor of a fast conductivity type;
• said solid state material pockets are semiconductor material pockets;
• at least one of the semiconductor pockets is a of a second conductivity type forming at least one PN junction region where the part of the substrate contacts the at least one semiconductor material pocket;
• and the PN junction region has a depth of less than 70 nanometers.

A mass-produced solid state device comprising:

• a solid state material substrate;
• at least one first solid state material pocket positioned on a first selected top surface of the substrate;
• and
• a solid state material layer less than three atomic layers thick and having at least one atomically smooth but curved major surface which intimately contacts uniformly the first selected surface of the substrate onto a first specified portion of the at least one first solid state material pocket and in which the solid state material layer is curved and has a rounded bottom of zero width to minimize thermal mismatch stresses.

A mass-produced solid state device comprising:

• a solid state material substrate;
• a left and a right adjacent solid state material pockets laterally separated by a gap and positioned on a common top surface of the substrate;
• a curved solid state material layer which:
• a) is less than 40 angstroms thick;
• b) is positioned on the common top surface of the substrate to bridge the gap between the two solid state material pockets;
• c) has a rounded bottom;
• and d) is a single-material solid state material layer selected from the group consisting of gate layer and field layer.