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US 6,784,491 B2Granted
MOS devices with reduced fringing capacitance
AssigneeIntel Corporation
InventorsBrian Doyle, Jack Kavalieros
Life of this patent
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Abstract
An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.
Claims5
A device comprising:
- a gate dielectric layer on a substrate, the substrate having a gate area, a source area and a drain area;
- a polysilicon layer on the gate dielectric layer at the gate area;
- two first gate spacers on the polysilicon layer, each having an arc-shaped gate sidewall facing inward;
- an interlevel dielectric (ILD) on the gate dielectric layer;
- and
- two second gate spacers fitting the first gate spacers and the polysilicon layer in the ILD.
3 more elements
Dependencies are inferred from the claim text.