Insulating barrier, NVM bandgap design
AssigneeInteruniversitair Micoroelektronica Centrum (IMEC, vzw)
InventorsPieter Blomme, Bogdan Govoreanu, Maarten Rosmeulen
Life of this patent
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Abstract
An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
Claims14
An insulating barrier extending between a first conductive region and a second conductive region, the insulating barrier for tunneling charge carriers from the first conductive region to the second conductive region, the insulating barrier comprising:
- a first portion contacting the first region;
- and
- a second portion contacting the first portion and extending towards the second region,
- wherein the first portion is substantially thinner than the second portion, the first portion comprising one or more dielectric materials for tunneling charge carriers and the second portion comprising one or more dielectric materials for tunneling charge carriers that are different than the one or more dielectric materials of the first portion, characterized in the one or more dielectric materials of the first portion having lower dielectric constants than the one or more dielectric materials of the second portion.
A memory device comprising an insulating barrier, the insulating barrier comprising:
- a first portion contacting a first conductive first region of the memory device;
- and
- a second portion contacting the first portion and extending towards a second conductive region of the memory device,
- wherein the first portion is substantially thinner than the second portion, the first portion comprising one or more dielectric materials and the second portion comprising one or more dielectric materials that are different than the one or more dielectric materials of the first portion, characterized in the one or more dielectric materials of the first portion having lower dielectric constants than the one or more dielectric materials of the second portion.
A memory device comprising:
- a semiconductor substrate having two heavily doped regions which are spaced by a channel region;
- a first insulating barrier on top of the channel region;
- a floating gate on top of the first insulating barrier;
- a second insulating barrier on top of the floating gate;
- and
- a control gate on top of the second insulating barrier,
- wherein the second insulating barrier comprises:
- a first portion contacting the floating gate;
- and
- a second portion contacting the first portion and extending towards the control gate,
- wherein the first portion is substantially thinner than the second portion, the first portion comprising one or more dielectric materials and the second portion comprising one or more dielectric materials that are different than the one or more dielectric materials of the first portion, characterized in the one or more dielectric materials of the first portion having lower dielectric constants than the one or more dielectric materials of the second portion, and
- wherein the one or more dielectric materials of the first and second portions and the thickness of the first and second portions are chosen such that, upon applying a voltage suitable for tunneling charge carriers through the second insulating barrier, the voltage drop across the first portion is higher than the voltage drop across the second portion.
Dependencies are inferred from the claim text.