Asymmetric band-gap engineered nonvolatile memory device

A gate stack for a nonvolatile memory cell, comprising:

• a Silicon Dioxide (SiO2) layer in contact with a channel region of the memory cell;
• a Tantalum Oxide (Ta2O5) layer in contact with the SiO2 layer;
• a charge-trapping floating plate in contact with the Ta2O5 layer;
• and
• a Zirconium Oxide (ZrO2) layer in contact with the charge-storage layer.

A nonvolatile memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a control gate of predetermined metallurgy;
• and
• a gate stack separating the control gate from the channel region, the gate stack including:
• a first insulator region including a Silicon Dioxide (SiO2) layer and a Tantalum Oxide (Ta2O5) layer;
• a floating charge-storage region separated from the channel region by the first insulator region;
• and
• a second insulator region including a Zirconium Oxide (ZrO2) layer, wherein the control gate is separated from the floating charge-storage region by the second insulator region;
• wherein the gate stack includes selected material for providing desired asymmetric energy barriers in conjunction with the control gate of predetermined metallurgy, and
• wherein the desired asymmetric energy barriers are adapted to:
• primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storage region, and
• retain a programmed charge in the floating charge-storage region.

A nonvolatile memory cell, comprising:

• a p− substrate;
• a first n type source/drain region and a second n type source/drain region separated by a channel region in the substrate;
• a Silicon Dioxide (SiO2) layer in contact with the channel region;
• a Tantalum Oxide (Ta2O5) layer in contact with the SiO2 layer;
• a charge-storage region in contact with the Ta2O5 layer;
• a Zirconium Oxide (ZrO2) layer in contact with the charge-storage layer;
• and
• an Aluminum control gate in contact with the ZrO2 layer.

A nonvolatile memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a control gate of predetermined metallurgy;
• a gate stack separating the control gate from the channel region, the gate stack including:
• a first insulator region including a Silicon Dioxide (SiO2) layer and a Tantalum Oxide (Ta2O5) layer;
• a floating plate separated from the channel region by the first insulator region, the floating plate including silicon nano crystals;
• and
• a second insulator region including a Zirconium Oxide (ZrO2) layer, wherein the control gate is separated from the floating charge-storage region by the second insulator region;
• wherein the gate stack includes selected material for providing desired asymmetric energy barriers in conjunction with the predetermined metallurgy of the control gate, and
• wherein the desired asymmetric energy barriers are adapted to:
• primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storing region, and
• retain a programmed charge in the floating charge-storage region.

A nonvolatile memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a control gate;
• and
• a gate stack separating the control gate from the channel region, the gate stack including:
• a first insulator region;
• a floating charge-storage region separated from the channel region by the first insulator region;
• and
• a second insulator region, wherein the control gate is separated from the floating charge-storage region by the second insulator region,
• wherein a hole energy barrier from the control gate to the second insulator region is sufficiently small such that a primary programming charge transport includes hole transport from the control gate to the floating charge-storage region upon application of a programming electromotive force (EMF) at the control gate that is positive with respect to the substrate.

A nonvolatile memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a control gate;
• and
• a gate stack separating the control gate from the channel region, the gate stack including:
• a first insulator region;
• a floating charge-storage region separated from the channel region by the first insulator region;
• and
• a second insulator region, wherein the control gate is separated from the floating charge-storage region by the second insulator region,
• wherein a hole energy barrier from the floating charge-storage region to the second insulator region and the equivalent oxide thicknesses of the second insulator region and the first insulator region are such that hole transport from the floating charge-storage region to the control gate is encouraged if an EMF transient is present at the substrate that is positive with respect to the control gate.

A nonvolatile memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region in a substrate;
• a control gate;
• and
• a gate stack separating the control gate from the channel region, the gate stack including:
• a first insulator region having a first equivalent oxide thickness;
• a floating charge-storage region separated from the channel region by the first insulator region;
• and
• a second insulator region having a second equivalent oxide thickness, wherein the control gate is separated from the floating charge-storage region by the second insulator region,
• wherein the equivalent oxide thickness of the first insulator region and the equivalent oxide thickness of the second insulator region is such that an electric field across the second insulator region is enhanced when a programming potential is applied across the control gate and the substrate,
• wherein the first insulator region and the second insulator region include materials that provide desired asymmetric energy barriers, and
• wherein the desired asymmetric energy barriers are adapted to:
• primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storage region, and
• retain a programmed charge in the floating charge-storage region.

A flash memory array, comprising:

• a number of nonvolatile memory cells, wherein each nonvolatile memory cell includes:
• a p− substrate;
• a first n type source/drain region and a second n type source/drain region separated by a channel region in the substrate;
• a Silicon Dioxide (SiO2) layer in contact with the channel region;
• a Tantalum Oxide (Ta2O5) layer in contact with the SiO2 layer;
• a charge-storage region in contact with the Ta2O5 layer;
• a Zirconium Oxide (ZrO2) layer in contact with the charge-storage layer;
• and
• an Aluminum control gate in contact with the ZrO2 layer;
• a number of source lines, each of the source lines being coupled to the first source/drain region of at least one of the memory cells;
• a number of control gate lines, each of the gate lines being coupled to the control gate of at least one of the memory cells;
• and
• a number of bit lines, each of the bit lines being coupled to the second source/drain region of at least one of the memory cells.

An electronic system, comprising:

• a processor;
• and
• a memory device adapted to communicate with the processor, wherein the memory device includes an array of flash memory cells, comprising:
• a number of nonvolatile memory cells, wherein each nonvolatile memory cell includes:
• a p− substrate;
• a first n type source/drain region and a second n type source/drain region separated by a channel region in the substrate;
• a Silicon Dioxide (SiO2) layer in contact with the channel region;
• a Tantalum Oxide (Ta2O5) layer in contact with the SiO2 layer;
• a charge-storage region in contact with the Ta2O5 layer;
• a Zirconium Oxide (ZrO2) layer in contact with the charge-storage layer;
• and
• an Aluminum control gate in contact with the ZrO2 layer;
• a number of source lines, each of the source lines being coupled to the first source/drain region of at least one of the memory cells;
• a number of control gate lines, each of the gate lines being coupled to the control gate of at least one of the memory cells;
• and
• a number of bit lines, each of the bit lines being coupled to the second source/drain region of at least one of the memory cells.

A method of forming a floating gate transistor, comprising:

• forming a first source/drain region and a second source/drain region separated by a channel region in a p− substrate;
• forming a gate stack over the channel region, including:
• forming an SiO2 layer on the channel region;
• forming a Ta2O5 layer on the SiO2 layer;
• forming a floating charge-storage region on the Ta2O5 layer;
• and
• forming a ZrO2 layer on the floating charge-storage region;
• and
• forming an aluminum control gate on the Ta2O5 layer.