Junction capacitor structure and fabrication method therefor in a dual damascene process

A method for forming an integrated circuit device comprising:

• providing a semiconductor substrate layer;
• forming first and second conductive vias within the semiconductor substrate layer;
• forming first and second conductive runners in an upper region of the semiconductor substrate layer overlying the first and said second conductive vias and in electrical contact therewith, respectively;
• forming a bottom capacitor plate over a top surface of the semiconductor substrate layer;
• forming a capacitor dielectric layer over the bottom capacitor plate;
• forming a top capacitor plate overlying the capacitor dielectric layer;
• forming a substrate dielectric layer;
• overlying the top capacitor plate;
• forming third and fourth conductive vias within the substrate dielectric layer, wherein the third and the fourth conductive vias overly and are in electrical connection with the first and the second conductive runners and the bottom and the top capacitor plates, respectively.