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US 6,784,470 B2Granted
Buffer, buffer operation and method of manufacture
AssigneeIntel Corporation
InventorJeffrey B. Davis
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.
Claims6
A semiconductor device comprising:
- a substrate of a first conductivity type;
- first and second wells of second conductivity type in the substrate;
- conductive material over a channel region of the substrate between the first and second wells;
- the conductive material operable under bias to apply an electric field to the channel region of the substrate to enhance carriers therein between the first and second wells;
- and
- a third well of first conductivity type within the first well;
- conductive material capacitively coupled to the third well;
- and
- the third well operable to receive a bias to apply an electric field to a depletion region of the first well and operable for depletion of carriers within the depletion region.
6 more elements
Dependencies are inferred from the claim text.