Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation

A method of manufacturing a semiconductor device, comprising sequential steps of:

• (a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof, said strained lattice semiconductor layer having a pre-sleeted amount of lattice strain therein;
• (b) forming a thin buffer/interfacial layer of a low-k dielectric material on said upper surface of said semiconductor substrate;
• and
• (c) forming a layer of a high-k dielectric material on said thin buffer/interfacial layer of a low-k dielectric material, wherein:
• steps (b) and (c) are each performed at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of said strained lattice semiconductor layer.