Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices

A method for forming back end of line (BEOL) interconnect structures in a magnetic random access memory (MRAM) device, the method comprising:

• defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level;
• forming a first dielectric layer over said array of MTJ stacks and said lower metallization level, and thereafter planarizing said first dielectric layer down to a top of said MTJ stacks;
• defining a via opening in said first dielectric layer, thereby exposing a portion of said lower metallization level;
• forming a second dielectric layer over said first dielectric layer and over said exposed portion of said lower metallization level;
• depositing a planar interlevel dielectric (ILD) layer over said second dielectric layer;
• and
• forming openings within said planar ILD layer and over said array of MTJ stacks and over said via opening.

A method for forming back end of line (BEOL) interconnect structures in a magnetic random access memory (MRAM) device, the method comprising:

• defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level;
• forming a passivation layer over said array of MTJ stacks and said lower metallization level;
• forming an encapsulating dielectric layer over said passivation layer, said encapsulating dielectric layer and said passivation layer planarized to a top of said MTJ stacks;
• forming a dielectric mask layer over said passivation layer, said encapsulating dielectric layer and said MTJ stacks;
• defining a via opening in said dielectric mask layer, thereby exposing a portion of said encapsulating dielectric layer;
• depositing a planar interlevel dielectric (ILD) layer over said dielectric mask layer;
• and
• forming openings within said planar ILD layer and over said array of MTJ stacks and over said via opening.