Transistor formation for semiconductor devices

A method of forming a pair of transistor gates of n-type and p-type conductivity during semiconductor fabrication comprising the steps of:

• forming transistor gate stack layers comprising a polysilicon layer having first and second lateral sections, the first lateral section having a dominant N+ type conductive dopant therein, the second lateral section having a dominant P+ type conductive dopant therein;
• etching the gate stack material and an upper portion of the polysilicon layer to form a first partial gate stack comprising an upper portion of the first lateral section and a second partial gate stack comprising an upper portion of the second lateral section, after the etching, a lower portion of the polysilicon layer remains to form a first lateral section extension beyond the first partial gate stack and a second lateral section extension beyond the second partial gate stack;
• forming a first mask that covers the partial second gate stack and the second lateral section extension and exposes the partial first gate stack and the first lateral section extension;
• with the first mask present, forming an N+ type conductive transistor gate by removing the exposed first lateral section extension;
• forming a second mask that covers the first-type conductive transistor gate and exposes the partial second gate stack and the second lateral section extension exposed;
• with the second mask present, forming a P+ type conductive transistor gate by removing the exposed second lateral section extension.

A method of forming a pair of transistors of opposite conductivity type during semiconductor fabrication comprising the steps of:

• forming transistor gate stack layers comprising a polysilicon layer having first and second lateral sections, the first lateral section having a dominant first-type conductive dopant therein, the second lateral section having a dominant second-type conductive dopant therein;
• etching the gate stack material and an upper portion of the polysilicon layer to form a first partial gate stack comprising an upper portion of the first lateral section and a second partial gate stack comprising an upper portion of the second lateral section, after the etching, a lower portion of the polysilicon layer remains to form a first lateral section extension beyond the first partial gate stack and a second lateral section extension beyond the second partial gate stack;
• forming a first mask that covers the partial second gate stack and the second lateral section extension and exposes the partial first gate stack and the first lateral section extension;
• with the first mask present, forming a first-type conductive transistor by removing the exposed first lateral section extension followed by forming source/drain regions dominated with the first-type conductive dopants;
• forming a second mask that covers the first-type conductive transistor and exposes the partial second gate stack and the second lateral section extension exposed;
• with the second mask present, forming a second-type conductive transistor by removing the exposed second lateral section extension followed by forming source/drain regions dominated with said second-type conductive dopants.

A method of forming a pair of complementary transistors during semiconductor fabrication of a memory device comprising the steps of:

• forming gate stack material comprising a gate oxide layer overlying a silicon substrate and a gate isolation region, a polysilicon layer overlying said gate oxide layer, the polysilicon layer having first and second lateral sections, the first lateral section having a dominant region of N+ type conductive dopants and the second lateral section having a dominant region of P+ type conductive dopants, a gate conductive layer overlying the polysilicon layer and a gate insulating layer overlying the gate conductive layer;
• etching the gate stack material and an upper portion of the polysilicon layer to form a first partial gate stack comprising an upper portion of the first lateral section and a second partial gate stack comprising an upper portion of the second lateral section, after the etching, a lower portion of the polysilicon layer remains to form a first lateral section extension beyond the first partial gate stack and a second lateral section extension beyond the second partial gate stack;
• forming a first mask that covers the partial second gate stack and the second lateral section extension and exposes the partial first gate stack and the first lateral section extension;
• with the first mask present, forming an N+ type conductive transistor by removing the exposed first lateral section extension followed by forming source/drain regions dominated with the N+ type conductive dopants;
• forming a second mask that covers the N+ type conductive transistor and exposes the partial second gate stack and the second lateral section extension exposed;
• with the second mask present, forming a P+ type conductive transistor by removing the exposed second lateral section extension followed by forming source/drain regions dominated with the P+ type conductive dopants.

A method of forming complementary transistors during semiconductor fabrication of a memory device comprising the steps of:

• performing an insitu dry etch of a P+ polysilicon layer and an N+ polysilicon layer to pattern and partially form a wordline pair comprising a partial N+ polysilicon wordline and a partial P+ polysilicon wordline by etching into but not through said P+ polysilicon layer and said N+ polysilicon layer such that a portion of said P+ polysilicon layer remains that extends beyond the partial P+ polysilicon wordline and a portion of the N+ polysilicon layer remains that extends beyond the partial N+ polysilicon wordline, said partial N+ polysilicon wordline further comprising a first tungsten material and a first oxide material and said partial P+ polysilicon wordline further comprising a second tungsten material and a second oxide material;
• masking said portion of said P+ polysilicon layer and said partial P+ polysilicon wordline and exposing said portion of said N+ polysilicon layer and said partial N+ polysilicon wordline;
• etching said exposed portion of said N+ polysilicon layer to form a complete N+ polysilicon wordline comprising said N+ polysilicon layer, said first tungsten material and said first oxide material;
• performing a first halo implant to form conductively doped halo regions for an n-channel transistor;
• performing a Source/Drain Extension (SDE) implant to form n-type conductive lightly doped drain regions for said n-channel transistor;
• masking said n-channel transistor and exposing said portion of said P+ polysilicon layer that extends beyond said partial P+ polysilicon wordline;
• etching said exposed portion of said P+ polysilicon layer to form a complete P+ polysilicon wordline profile comprising said P+ polysilicon layer, said second tungsten material, and said second oxide material;
• performing a second halo implant to form conductively doped halo regions for an p-channel transistor.