Method for fabricating semiconductor device
AssigneeHynix Semiconductor Inc.
InventorSung-Kwon Lee
Life of this patent
Estimating the term…
Abstract
The present invention provides a method for fabricating a semiconductor device capable of preventing a pattern at an edge area of a wafer from being lifted and acting as a particle source. The present invention includes the steps of: preparing a wafer having a first area and a second area, wherein the first area has lower topology than the second area; forming a target layer on the wafer; and patterning the target layer through a photolithography process so to form a number of first patterns in a line shape at the second area and to form a number of second patterns in a closed loop shape at the first area.
Claims15
A method for fabricating a semiconductor device, comprising the steps of:
- preparing a wafer having a first area and a second area, wherein the first area has lower topology than the second area;
- forming a conductive layer on the wafer;
- and
- patterning the conductive layer through a photolithography process so to form a number of conductive patterns in a line shape at the second area and a number of dummy conductive patterns in a closed loop configuration at the first area,
- wherein the first area is an edge area of the wafer.
The method as recited in wherein, in the step of patterning the conductive layer, the conductive layer in the second area is removed by about 30% to about 50% of the total area of the second area.
A method for fabricating a semiconductor device, comprising the steps of:
- forming a number of word lines on a wafer having a first area and a second area;
- forming an insulating layer on the wafer and the word line;
- forming a contact hole by selectively etching the insulating layer;
- forming a first conductive layer on the insulating layer including the contact hole;
- forming a plug in the contact hole through a polishing of the first conductive layer, thereby obtaining the first area having a lower topology than the second area;
- forming a second conductive layer on the wafer including the plug;
- patterning the second conductive layer through a photolithography process so to form a number of first patterns in a line shape at the first area and to form a number of dummy patterns in a closed loop shape at the second area;
- forming an insulating layer on the wafer including the first and second patterns;
- and
- planarizing the insulating layer.
Dependencies are inferred from the claim text.