Microchannel formation for fuses, interconnects, capacitors, and inductors
AssigneeLSI Logic Corporation
InventorsDavid T. Price, Jayashree Kalpathy-Cramer
Life of this patent
Estimating the term…
Abstract
The present invention provides a method for forming interconnect lines and conductors and passive devices in the fabrication of an integrated circuit. A gap is created in the patterning of a first layer. The gap is filled by a dielectric material so that an encapsulated conduit is formed in the gap. The encapsulated conduit is filled with a conductor by chemical vapor deposition processes or other deposition processes, the filling facilitated by forming via holes to intersect the conduit, and then filling the via holes. The conductor filled conduit can be used as a resistor, fuse, inductor, or capacitor.
Claims21
A method of forming a conductive line on a semiconductor wafer, the method comprising:
- forming a trench on the semiconductor wafer;
- depositing a dielectric material in the trench so that a hollow enclosed conduit is formed within the dielectric material in the trench;
- and
- forming at least one via hole in the dielectric material deposited in the trench and configured to intersect the hollow enclosed conduit;
- and
- filling the hollow conduit by using the at least one via hole to thereby form the conductive line.
A method of forming a signal transmission line on a semiconductor wafer, the method comprising:
- forming a channel within a first layer on the semiconductor wafer;
- depositing a dielectric material in the channel, wherein the dielectric material and the channel configurations are selected so that a hollow enclosed conduit is formed in the channel;
- forming at least one via hole in the dielectric material deposited in the channel and configured to intersect the hollow enclosed conduit;
- and
- filling the via hole and the hollow enclosed conduit with a first material to thereby form the signal transmission line, whereby the first material is one of a dielectric and a conductor.
A semiconductor integrated circuit formed by:
- forming a channel within a first layer on a semiconductor wafer;
- depositing a dielectric material in the channel, wherein the dielectric material and the channel configurations are selected so that a hollow enclosed conduit is formed in the channel;
- forming at least one via hole in the dielectric material deposited in the channel and configured to intersect the hollow enclosed conduit;
- and
- filling via hole and the hollow enclosed conduit with a first conductive material to form a conductive metal line.
Dependencies are inferred from the claim text.