Methods for forming aligned fuses disposed in an integrated circuit

A method of forming a semiconductor device on a substrate, the method comprising:

• forming a first conductive layer over the substrate;
• forming a first fuse region in the first conductive layer;
• forming an insulating layer on the first conductive layer including the fuse region;
• forming a second conductive layer on the insulating layer;
• forming a second fuse region in the second conductive layer, at least a portion of the second fuse region overlapping the first fuse region;
• forming MOS transistors on the substrate;
• and
• interconnecting each of the first and second fuse regions with a respective MOS transistor.

A method of operating a semiconductor memory device formed on a substrate, the memory device including an array of memory cells including primary and redundant memory cells, and the memory device further including read/write and address circuitry, the method comprising:

• forming a first group of fuses in a first conductive layer over the substrate, the first group of fuses occupying a first area of the first conductive layer;
• forming an insulating layer on the first conductive layer;
• forming a second conductive layer on the insulating layer;
• and
• forming a second group of fuses in the second conductive layer, the second group of fuses occupying a second area of the second conductive layer and being positioned to at least partially overlap the first area;
• selectively programming the fuses in the first and second groups;
• receiving and decoding addresses corresponding to memory cells in the array;
• and
• for each address, accessing either primary or redundant memory cells corresponding to the address responsive to the states of the programmed fuses.

A method of forming fuse elements in a semiconductor integrated circuit formed on a substrate, the method comprising:

• forming a first conductive layer over the substrate;
• forming a plurality of independent conductive regions in the first conductive layer, each region being electrically isolated from the other regions and corresponding to a first fuse element;
• forming an insulating layer on the first conductive layer;
• forming a second conductive layer on the insulating layer;
• and
• forming a plurality of independent conductive regions in the second conductive layer, each region being electrically isolated from the other regions and corresponding to a second fuse element, and at least one of the second fuse elements being positioned to at least partially overlap a first fuse element or elements in the first conductive layer.