Method for making semiconductor device
AssigneesFujitsu Limited, Fujitsu Quantum Devices Limited
InventorsKozo Makiyama, Katsumi Ogiri
Life of this patent
Estimating the term…
Abstract
A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding over an undercut in an underlying layer, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.
Claims14
A method for making a semiconductor device comprising:
- forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern comprising a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding over an undercut in an underlying layer, wherein corners of the second opening at the tip of the over-gate section in a plan view are arc-shaped;
- and
- forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.
A method for making a semiconductor device comprising:
- forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern comprising a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding over an undercut in an underlying layer, wherein corners of the second opening at the tip of the over-gate section in a plan view are selectively subjected to multiple exposure;
- and
- forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.
Dependencies are inferred from the claim text.