Method of fabrication of stacked semiconductor devices
AssigneeMicron Technology, Inc.
InventorMichael B. Ball
Life of this patent
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Abstract
A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair.
Claims10
A method of fabricating a multi-level stack of semiconductor substrate elements, each semiconductor substrate element of the substrate elements including integrated circuitry, comprising:
- providing a first semiconductor substrate element having a first side including integrated circuitry thereon and having a back side in a first wafer having a periphery having a portion thereof including a flat;
- providing a second semiconductor substrate element having a first side including integrated circuitry thereon and having a back side in a second wafer having a periphery having a portion thereof including a flat;
- providing a heat sink element for the multi-level stack between the first and second semiconductor substrate elements;
- stacking the first semiconductor substrate element and the second semiconductor substrate element in a superimposed relationship having the back side of the first semiconductor substrate element facing the back side of the second semiconductor substrate element having the periphery of the first semiconductor substrate element substantially aligned with the periphery of the second semiconductor substrate element, the first semiconductor substrate element and the second semiconductor substrate element for locating a portion of the integrated circuitry on the first semiconductor substrate element vertically spaced from a portion of the integrated circuitry on the second semiconductor substrate element for vertical alignment of the first semiconductor substrate element and the second semiconductor substrate element;
- and
- severing from the multi-stack stack traversely at least one dice pair comprising a die from the first semiconductor substrate element and a second die from the second semiconductor substrate element;
- and
- adhesively attaching the first semiconductor substrate element and the second semiconductor substrate element.
Dependencies are inferred from the claim text.