Method of protecting a passivation layer during solder bump formation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Yu Wang, Chender Huang, Pei-Haw Tsao, Ken Chen, Hank Huang
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Yu Wang, Chender Huang, Pei-Haw Tsao, Ken Chen, Hank Huang
Estimating the term…
A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.
A method for protecting a passivation layer during a solder bump formation process comprising the steps of:
A method for protecting a passivation layer with under bump metallization (UBM) during a solder bump formation process comprising the steps of:
Dependencies are inferred from the claim text.