IC layout system having separate trial and detailed routing phases

Computer readable media storing software which when executed by a computer causes the computer to carry out a method for designing a layout for an integrated circuit (IC) comprising cells having terminals interconnected by nets, wherein the layout includes a placement plan and a routing plan, wherein the placement plan specifies a position of each cell within in a semiconductor substrate, and wherein the routing plan specifies routing of the nets between terminals of the cells, the method comprising the steps of:

• a. a generating a placement plan for the IC specifying a position within the semiconductor substrate for each of the cells,
• b. generating a trial routing plan specifying an approximate routing of each net,
• c. modifying the placement plan and trial routing plan that to reposition at least one cell to reroute at least one net and to insert at least one additional buffer into at least one of the nets, so that the placement and routing plans satisfy first constraints, including constraints on signal path delays through the nets,
• d. converting the trial routing plan into a detailed routing plan specifying a detailed routing of each net, and
• e. modifying the placement plan and the detailed routing plan so that they satisfy second constraints.

The computer readable media in accordance with claim a further comprising the step of:

• f. between steps b and d, generating a clock tree design for a clock tree to be included in the IC for delivering a clock signal to various ones of the cells, the clock tree including set of buffers interconnected by nets;
• g. between steps f and d, modifying the placement plan to specify a position within the semiconductor substrate of each buffer of the clock tree and modifying the trial placement plan so that it specifies approximate routing of the nets interconnecting the buffers;
• h. following step d, modifying the clock tree design;
• and
• i. modifying the placement plan and the detailed routing plan to render them consistent with changes to the clock tree design made at step f.

An apparatus for designing a layout for an integrated circuit (IC) comprising cells having terminals interconnected by nets, wherein the layout includes a placement plan and a routing plan, wherein the placement plan specifies a position of each cell within a semiconductor substrate, and wherein the routing plan specifies routing of the nets between terminals of the cells they interconnect, the apparatus comprising:

• at least one computer, and computer readable-media containing software read accessed and executed by the computer causing the computer to carry out the steps of:
• a. generating a placement plan for the IC specifying a position within the semiconductor substrate for each of the cells,
• b. generating a trial routing plan specifying an approximate route each net is to follow,
• c. iteratively modifying the placement plan generated at step a and the trial routing plan generated at step b to reposition at least one cell, to reroute at least one net, and to insert at least one additional buffer into at least one of the nets, until the placement and routing plans satisfy first constraints, including constraints on signal path delays through the nets,
• d. converting the trial routing plan iteratively modified at step c into a detailed routing plan specifying a detailed route each net is to follow between the cell terminals it interconnects, and
• e. iteratively modifying the placement plan and the detailed routing plan until they satisfy second constraints.