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US 6,780,747 B2Granted
Methods for providing void-free layers for semiconductor assemblies
AssigneeTessera, Inc.
InventorsThomas H. Distefano, Joseph Fjelstad
Life of this patent
Estimating the term…
Abstract
A method of providing a substantially void free layer for one or more flip chip assemblies, or one or more microelectronic components, utilizing a curable encapsulant. Also disclosed is a method of injecting an encapsulant into an assembly and a method of treating a microelectronic component to form a void free layer.
Claims27
A method of manufacturing a semiconductor package comprising:
- (a) attaching a semiconductor chip having bonding pads along a central line on an active surface of the semiconductor chip to a tape wiring substrate, wherein an elastomer interposes between the active surface of the semiconductor chip and the tape wiring substrate, and the tape wiring substrate comprises an opening, a plurality of beam leads which are exposed through the opening of the tape wiring substrate, a plurality of terminal pads which are extensions of the beam leads, and a plurality of via holes through which the terminal pads are exposed;
- (b) bonding the beam leads to the bonding pads which are exposed through the openings of the tape wiring substrate and the elastomer;
- (c) attaching a cover film to a tap surface of the tape wiring substrate and turning the top surface down;
- (d) encapsulating the opening and side surfaces of the elastomer and the semiconductor chip with an encapsulant, wherein the encapsulating comprises:
- (d-1) dispensing the encapsulant on a portion of the tape wiring substrate that is close to one end of the openings of the elastomer so that the encapsulant can flow into and fill the opening from the one end;
- and
- (d-2) dispensing the encapsulant on the tape wiring substrate along a perimeter of the semiconductor chip so that the encapsulant can cover side surfaces of the elastomer and the semiconductor chip;
- and
- (e) curing the encapsulant and removing the cover film from the tape wiring substrate.
6 more elements
A method of manufacturing a semiconductor package comprising:
- (a) attaching a semiconductor chip having bonding pads along a central line on an active surface of the semiconductor chip to a tape wiring substrate, wherein a compliant layer having an opening interposes between the active surface of the semiconductor chip and the tape wiring substrate, and the tape wiring substrate comprises an opening, a plurality of beam leads which are aligned with the opening of the tape wiring substrate, and a plurality of terminal pads which are extensions of the beam leads;
- (b) bonding the beam leads to the bonding pads which are exposed through the openings of the tape wiring substrate and the compliant layer;
- (c) attaching a cover film to a top surface of the tape wiring substrate and turning the top surface down;
- (d) encapsulating the openings and side surfaces of the elastomer and the semiconductor chip with an encapsulant, wherein the encapsulating comprises:
- (d-1) dispensing the encapsulant on a portion of the tape wiring substrate that is close to one end of the opening of the compliant layer so that the encapsulant can flow into and fill the opening from the one end;
- and
- (d-2) dispensing the encapsulant on the tape wiring substrate along a perimeter of the semiconductor chip so that the encapsulant can cover side surfaces of the compliant layer and the semiconductor chip;
- and
- (e) curing the encapsulant.
6 more elements
A method of making a chip scale package comprising the steps of:
- (a) providing a substrate having an upper surface, a lower surface, and a slot defined therein, the substrate being provided with a plurality of solder pads on the upper surface thereof and a plurality of leads within the slot, wherein the substrate has a plurality of through-holes corresponding to the solder pads, and each of the leads has at least one end electrically connected to the corresponding solder pad;
- (b) attaching two individual elastomer pads respectively onto the upper surface of the substrate in a manner that each of the two individual elastomer pads flanks the slot of the substrate at a predetermined distance from the slot;
- (c) providing a semiconductor chip having a plurality of bonding pads centrally formed thereon;
- (d) attaching the semiconductor chip onto the upper surface of the substrate in a manner that the bonding pads are exposed from the slot of the substrate;
- (e) electrically coupling the leads of the substrate to the bonding pads of the semiconductor chip in a manner that each of the leads is electrically connected to the corresponding bonding pad;
- and
- (f) forming a package body having a first portion on the upper surface of the substrate around the chip and a second portion within the slot of the substrate, wherein the first portion and the second portion are formed substantially at the same time.
4 more elements
A method of making a chip scale package comprising the steps of:
- (a) providing a substrate having an upper surface, a lower surface, and a slot defined therein, the substrate being provided with a plurality of solder pads and a plurality of leads within the slot, wherein each of the leads has at least one end electrically connected to the corresponding solder pad;
- (b) attaching two individual compliant pads respectively onto the upper surface of the substrate in a manner that each of the two individual compliant pads flanks the slot of the substrate at a predetermined distance from the slot;
- (c) providing a semiconductor chip having a plurality of bonding pads centrally formed thereon;
- (d) attaching the semiconductor chip onto the upper surface of the substrate in a manner that the bonding pads are exposed from the slot of the substrate;
- (e) electrically coupling the leads of the substrate to the bonding pads of the semiconductor chip in a manner that each of the leads is electrically connected to the corresponding bonding pad;
- and
- (f) forming a package body having a first portion on the upper surface of the substrate around the chip and a second portion within the slot of the substrate, wherein the first portion and the second portion are formed substantially at the same time.
4 more elements
Dependencies are inferred from the claim text.