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US 6,775,800 B2Granted
System and method for high speed processing of turbo codes
AssigneeIcoding Technology, Inc.
InventorsBrian S. Edmonston, Paul K. Gray
Life of this patent
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Abstract
A system and method for high efficiency, high performance processing of turbo codes is described. In accordance with one embodiment of the invention, an interleaver for interleaving code symbols is providing, the interleaver having a plurality of subsections, each subsection having a set of addresses and each address having an index, wherein a substantially constant relationship exists from any one subsection to any other subsection between the index of each address at a particular location.
Claims24
A forward error correction encoder comprising:
- a first encoder adapted to encode information bits;
- a pseudo-random interleaver adapted to pseudo-randomly interleave code symbols from said first encoder, said interleaver having a plurality of subsections, each subsection having a set of addresses, and each address having an index, wherein a substantially constant relationship exists from any one subsection to any other subsection between the index of each address at a particular location;
- and
- a second encoder adapted to encode interleaved code symbols from said interleaver.
1 more element
A forward error correction decoding apparatus comprising:
- an interleaver configured to interleave code symbols from a first encoder, said interleaver having a plurality of subsections, each subsection having a set of addresses, and each address having an memory index, wherein a substantially constant relationship exists from any one subsection to any other subsection between the memory index of each address at a particular location;
- a plurality of memory elements, each capable of storing data associated with a valid memory index value;
- and
- a plurality of decoders, each capable of decoding a subsection from said interleaver.
1 more element
A forward error correction decoding apparatus comprising:
- a plurality of memory elements, each capable of storing data associated with a valid index value;
- a plurality of decoders, each capable of decoding a subsection from said interleaver;
- and
- M interleaver subsections, where said M interleaver subsections each have addresses and said addresses are generated in sets of n values separated by a value SET_STEP, and wherein each subsection is comprised of r sets of n values, where r is an integer multiple of M.
1 more element
A system adapted to perform iterative decoding comprising:
- an address vector generation circuit adapted to generate a vector of M interleaver addresses;
- a routing selector circuit adapted to calculate a routing index based on an address from said address vector;
- a set of memories, each adapted to store extrinsic information for a portion of a frame being decoded;
- an address routing circuit adapted to route said address vector to said set of memories according to said routing index;
- and
- a data routing circuit adapted to route data from said set of memories to a set of decoders each of which decodes a portion of the frame in parallel;
- wherein the routing index for each address in said address vector is unique.
4 more elements
A decoding apparatus adapted to decode parallel concatenated convolutional codes and serial concatenated convolutional codes comprising:
- a decoder adapted to perform the maximum a posteriori decoding algorithm, said decoder having a source data input and an extrinsic information input;
- a sample memory adapted to store receive samples;
- an extrinsic information memory adapted to store extrinsic information and soft decision information, said extrinsic information memory coupled to said extrinsic information input of said decoder;
- and
- a multiplexer adapted to couple said sample memory to said source data input in a first mode, and coupling said extrinsic information memory to said source data input in a second mode.
2 more elements
A decoding apparatus for decoding parallel concatenated convolutional codes and serial concatenated convolutional codes comprising:
- a plurality of decoders adapted to perform the maximum a posteriori decoding algorithm, said decoder having a source data input and an extrinsic information input;
- a plurality of sample memories adapted to store receive samples;
- a plurality of extrinsic information memory adapted to store extrinsic information and soft decision information, said extrinsic information memory coupled to said extrinsic information input of said decoder;
- and
- a multiplexer adapted to couple said sample memory to said source data input in a first mode, and coupling said extrinsic information memory to said source data input in a second mode.
2 more elements
A forward error correction decoder comprising:
- an interleaver for interleaving code symbols from an encoder, said interleaver having a plurality of subsections, each subsection having a set of addresses, and each address having an index, wherein a constant relationship exists, from any subsection to another subsection, between addresses at the same location;
- a plurality of memory elements, each for storing data associated with a valid index value;
- and
- a plurality of subsection decoders, each for decoding a subsection from said interleaver;
- wherein said index comprises a subset of bits from said address.
2 more elements
A forward error correction decoder comprising:
- an interleaver for interleaving code symbols from an encoder, said interleaver having a plurality of subsections, each subsection having a set of addresses, and each address having an index, wherein a constant relationship exists, from any subsection to another subsection, between addresses at the same location;
- a plurality of memory elements, each for storing data associated with a valid index value;
- and
- a plurality of subsection decoders, each for decoding a subsection from said interleaver;
- wherein said index comprises said address divided by a row size.
2 more elements
A forward error correction decoder comprising:
- a plurality of memory elements each for storing data associated with a valid index value, said valid index value comprising trunc(A/r*SET_STEP) % M, each of said memory elements corresponding to a possible index value, and wherein data corresponding to a write address is written to a memory element associated with an index corresponding to said write address;
- a plurality of subsection decoders, each for decoding a subsection from said interleaver;
- and
- M interleaver subsections, where said M interleaver subsections each have addresses and said addresses are generated in sets of n values separated by a value SET_STEP, and wherein each subsection is comprised of r sets of n values, where r is an integer multiple of M.
1 more element
Apparatus for performing iterative decoding comprising:
- means for generating vector of M interleaver addresses;
- means for calculating a routing index based on an address from said address vector;
- memory means for storing extrinsic information for a portion of a frame being decoded;
- means for routing said address vector to said set of memories according to said routing index;
- and
- means for routing data from said set of memories to a set of decoders each of which decodes a portion of the frame in parallel;
- wherein the routing index for each address in said address vector is unique.
4 more elements
Apparatus adapted to perform iterative decoding, comprising:
- circuitry adapted to generate a vector comprising M interleaver addresses;
- circuitry adapted to calculate a routing index based on an address from said address vector;
- memory apparatus adapted to store extrinsic information for a portion of a frame being decoded;
- circuitry adapted to route said address vector to said memory apparatus according to said routing index;
- and
- circuitry adapted to route data from memory apparatus to a set of decoders which decode a portion of the frame in parallel;
- wherein the routing index for each address in said address vector is unique.
4 more elements
Apparatus for decoding parallel concatenated convolutional codes and serial concatenated convolutional codes comprising:
- means for performing the maximum a posteriori decoding algorithm, said means having a source data input and an extrinsic information input;
- means for storing receive samples;
- means for storing extrinsic information and soft decision information, said means for storing extrinsic information coupled to said extrinsic information input of said means for performing;
- and
- means for coupling said means for storing receive samples to said source data input in a first mode, and coupling said means for storing extrinsic information to said source data input in a second mode.
2 more elements
A forward error correction decoder comprising:
- means for interleaving code symbols from an encoder, said means having a plurality of subsections, each subsection having a set of addresses, and each address having an index, wherein a constant relationship exists, from any subsection to another subsection, between addresses at the same location;
- means for storing data associated with a valid index value;
- and
- a plurality of decoding means, each for decoding a subsection from said means for interleaving;
- wherein said index comprises said address divided by a row size.
2 more elements
Dependencies are inferred from the claim text.